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Searched refs:VIA_PCI_DMA_CSR0 (Results 1 – 3 of 3) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/via/
Dvia_dmablit.c216 via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DD | VIA_DMA_CSR_TD | in via_fire_dmablit()
222 via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DE | VIA_DMA_CSR_TS); in via_fire_dmablit()
223 via_read(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04); in via_fire_dmablit()
291 via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TA); in via_abort_dmablit()
299 via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TD | VIA_DMA_CSR_DD); in via_dmablit_engine_off()
330 ((status = via_read(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04)) & VIA_DMA_CSR_TD); in via_dmablit_handler()
349 via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TD); in via_dmablit_handler()
Dvia_dmablit.h112 #define VIA_PCI_DMA_CSR0 0xE90 /* Command/Status Register of Channel 0 */ macro
Dvia_irq.c75 {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
84 {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,