| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | gfxhub_v1_0.c | 184 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v1_0_enable_system_domain()
185 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); in gfxhub_v1_0_enable_system_domain()
186 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, in gfxhub_v1_0_enable_system_domain()
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| D | mmhub_v1_0.c | 203 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in mmhub_v1_0_enable_system_domain()
204 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); in mmhub_v1_0_enable_system_domain()
205 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, in mmhub_v1_0_enable_system_domain()
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| D | gmc_v7_0.c | 660 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gmc_v7_0_gart_enable()
661 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); in gmc_v7_0_gart_enable()
662 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v7_0_gart_enable()
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| D | gmc_v8_0.c | 909 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gmc_v8_0_gart_enable()
910 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); in gmc_v8_0_gart_enable()
911 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v8_0_gart_enable()
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| D | sid.h | 393 #define VM_CONTEXT0_CNTL 0x504 macro
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| /kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
| D | rv770.c | 932 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in rv770_pcie_gart_enable()
937 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); in rv770_pcie_gart_enable()
954 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); in rv770_pcie_gart_disable()
1005 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); in rv770_agp_enable()
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| D | rv770d.h | 634 #define VM_CONTEXT0_CNTL 0x1410 macro
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| D | nid.h | 127 #define VM_CONTEXT0_CNTL 0x1410 macro
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| D | ni.c | 1311 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in cayman_pcie_gart_enable()
1368 WREG32(VM_CONTEXT0_CNTL, 0); in cayman_pcie_gart_disable()
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| D | r600.c | 1172 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in r600_pcie_gart_enable()
1177 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); in r600_pcie_gart_enable()
1194 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); in r600_pcie_gart_disable()
1260 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); in r600_agp_enable()
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| D | sid.h | 392 #define VM_CONTEXT0_CNTL 0x1410 macro
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| D | cikd.h | 510 #define VM_CONTEXT0_CNTL 0x1410 macro
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| D | evergreen.c | 2441 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in evergreen_pcie_gart_enable()
2460 WREG32(VM_CONTEXT0_CNTL, 0); in evergreen_pcie_gart_disable()
2510 WREG32(VM_CONTEXT0_CNTL, 0); in evergreen_agp_enable()
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| D | evergreend.h | 1136 #define VM_CONTEXT0_CNTL 0x1410 macro
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| D | r600d.h | 573 #define VM_CONTEXT0_CNTL 0x1410 macro
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| D | si.c | 4322 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in si_pcie_gart_enable()
4387 WREG32(VM_CONTEXT0_CNTL, 0); in si_pcie_gart_disable()
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| D | cik.c | 5466 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in cik_pcie_gart_enable()
5560 WREG32(VM_CONTEXT0_CNTL, 0); in cik_pcie_gart_disable()
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