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1 /*
2  * Copyright (c) 2013 Eugene Krasnikov <k.eugene.e@gmail.com>
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #ifndef _WCN36XX_H_
18 #define _WCN36XX_H_
19 
20 #include <linux/completion.h>
21 #include <linux/printk.h>
22 #include <linux/spinlock.h>
23 #include <net/mac80211.h>
24 
25 #include "hal.h"
26 #include "smd.h"
27 #include "txrx.h"
28 #include "dxe.h"
29 #include "pmc.h"
30 #include "debug.h"
31 
32 #define WLAN_NV_FILE               "wlan/prima/WCNSS_qcom_wlan_nv.bin"
33 #define WCN36XX_AGGR_BUFFER_SIZE 64
34 
35 extern unsigned int wcn36xx_dbg_mask;
36 
37 enum wcn36xx_debug_mask {
38 	WCN36XX_DBG_DXE		= 0x00000001,
39 	WCN36XX_DBG_DXE_DUMP	= 0x00000002,
40 	WCN36XX_DBG_SMD		= 0x00000004,
41 	WCN36XX_DBG_SMD_DUMP	= 0x00000008,
42 	WCN36XX_DBG_RX		= 0x00000010,
43 	WCN36XX_DBG_RX_DUMP	= 0x00000020,
44 	WCN36XX_DBG_TX		= 0x00000040,
45 	WCN36XX_DBG_TX_DUMP	= 0x00000080,
46 	WCN36XX_DBG_HAL		= 0x00000100,
47 	WCN36XX_DBG_HAL_DUMP	= 0x00000200,
48 	WCN36XX_DBG_MAC		= 0x00000400,
49 	WCN36XX_DBG_BEACON	= 0x00000800,
50 	WCN36XX_DBG_BEACON_DUMP	= 0x00001000,
51 	WCN36XX_DBG_PMC		= 0x00002000,
52 	WCN36XX_DBG_PMC_DUMP	= 0x00004000,
53 	WCN36XX_DBG_TESTMODE		= 0x00008000,
54 	WCN36XX_DBG_TESTMODE_DUMP	= 0x00010000,
55 	WCN36XX_DBG_ANY		= 0xffffffff,
56 };
57 
58 #define wcn36xx_err(fmt, arg...)				\
59 	printk(KERN_ERR pr_fmt("ERROR " fmt), ##arg)
60 
61 #define wcn36xx_warn(fmt, arg...)				\
62 	printk(KERN_WARNING pr_fmt("WARNING " fmt), ##arg)
63 
64 #define wcn36xx_info(fmt, arg...)		\
65 	printk(KERN_INFO pr_fmt(fmt), ##arg)
66 
67 #define wcn36xx_dbg(mask, fmt, arg...) do {			\
68 	if (wcn36xx_dbg_mask & mask)					\
69 		printk(KERN_DEBUG pr_fmt(fmt), ##arg);	\
70 } while (0)
71 
72 #define wcn36xx_dbg_dump(mask, prefix_str, buf, len) do {	\
73 	if (wcn36xx_dbg_mask & mask)					\
74 		print_hex_dump(KERN_DEBUG, pr_fmt(prefix_str),	\
75 			       DUMP_PREFIX_OFFSET, 32, 1,	\
76 			       buf, len, false);		\
77 } while (0)
78 
79 enum wcn36xx_ampdu_state {
80 	WCN36XX_AMPDU_NONE,
81 	WCN36XX_AMPDU_INIT,
82 	WCN36XX_AMPDU_START,
83 	WCN36XX_AMPDU_OPERATIONAL,
84 };
85 
86 #define HW_VALUE_PHY_SHIFT 8
87 #define HW_VALUE_PHY(hw_value) ((hw_value) >> HW_VALUE_PHY_SHIFT)
88 #define HW_VALUE_CHANNEL(hw_value) ((hw_value) & 0xFF)
89 #define WCN36XX_HW_CHANNEL(__wcn)\
90 	HW_VALUE_CHANNEL(__wcn->hw->conf.chandef.chan->hw_value)
91 #define WCN36XX_BAND(__wcn) (__wcn->hw->conf.chandef.chan->band)
92 #define WCN36XX_CENTER_FREQ(__wcn) (__wcn->hw->conf.chandef.chan->center_freq)
93 #define WCN36XX_LISTEN_INTERVAL(__wcn) (__wcn->hw->conf.listen_interval)
94 #define WCN36XX_FLAGS(__wcn) (__wcn->hw->flags)
95 #define WCN36XX_MAX_POWER(__wcn) (__wcn->hw->conf.chandef.chan->max_power)
96 
97 #define RF_UNKNOWN	0x0000
98 #define RF_IRIS_WCN3620	0x3620
99 #define RF_IRIS_WCN3680	0x3680
100 
buff_to_be(u32 * buf,size_t len)101 static inline void buff_to_be(u32 *buf, size_t len)
102 {
103 	int i;
104 	for (i = 0; i < len; i++)
105 		buf[i] = cpu_to_be32(buf[i]);
106 }
107 
108 struct nv_data {
109 	int	is_valid;
110 	u8	table;
111 };
112 
113 /**
114  * struct wcn36xx_vif - holds VIF related fields
115  *
116  * @bss_index: bss_index is initially set to 0xFF. bss_index is received from
117  * HW after first config_bss call and must be used in delete_bss and
118  * enter/exit_bmps.
119  */
120 struct wcn36xx_vif {
121 	struct list_head list;
122 	u8 dtim_period;
123 	enum ani_ed_type encrypt_type;
124 	bool is_joining;
125 	bool sta_assoc;
126 	struct wcn36xx_hal_mac_ssid ssid;
127 	enum wcn36xx_hal_bss_type bss_type;
128 
129 	/* Power management */
130 	enum wcn36xx_power_state pw_state;
131 
132 	u8 bss_index;
133 	/* Returned from WCN36XX_HAL_ADD_STA_SELF_RSP */
134 	u8 self_sta_index;
135 	u8 self_dpu_desc_index;
136 	u8 self_ucast_dpu_sign;
137 
138 	struct list_head sta_list;
139 };
140 
141 /**
142  * struct wcn36xx_sta - holds STA related fields
143  *
144  * @tid: traffic ID that is used during AMPDU and in TX BD.
145  * @sta_index: STA index is returned from HW after config_sta call and is
146  * used in both SMD channel and TX BD.
147  * @dpu_desc_index: DPU descriptor index is returned from HW after config_sta
148  * call and is used in TX BD.
149  * @bss_sta_index: STA index is returned from HW after config_bss call and is
150  * used in both SMD channel and TX BD. See table bellow when it is used.
151  * @bss_dpu_desc_index: DPU descriptor index is returned from HW after
152  * config_bss call and is used in TX BD.
153  * ______________________________________________
154  * |		  |	STA	|	AP	|
155  * |______________|_____________|_______________|
156  * |    TX BD     |bss_sta_index|   sta_index   |
157  * |______________|_____________|_______________|
158  * |all SMD calls |bss_sta_index|   sta_index	|
159  * |______________|_____________|_______________|
160  * |smd_delete_sta|  sta_index  |   sta_index	|
161  * |______________|_____________|_______________|
162  */
163 struct wcn36xx_sta {
164 	struct list_head list;
165 	struct wcn36xx_vif *vif;
166 	u16 aid;
167 	u16 tid;
168 	u8 sta_index;
169 	u8 dpu_desc_index;
170 	u8 ucast_dpu_sign;
171 	u8 bss_sta_index;
172 	u8 bss_dpu_desc_index;
173 	bool is_data_encrypted;
174 	/* Rates */
175 	struct wcn36xx_hal_supported_rates_v1 supported_rates;
176 
177 	spinlock_t ampdu_lock;		/* protects next two fields */
178 	enum wcn36xx_ampdu_state ampdu_state[16];
179 	int non_agg_frame_ct;
180 };
181 struct wcn36xx_dxe_ch;
182 struct wcn36xx {
183 	struct ieee80211_hw	*hw;
184 	struct device		*dev;
185 	struct list_head	vif_list;
186 
187 	const struct firmware	*nv;
188 
189 	u8			fw_revision;
190 	u8			fw_version;
191 	u8			fw_minor;
192 	u8			fw_major;
193 	u32			fw_feat_caps[WCN36XX_HAL_CAPS_SIZE];
194 	bool			is_pronto;
195 
196 	/* extra byte for the NULL termination */
197 	u8			crm_version[WCN36XX_HAL_VERSION_LENGTH + 1];
198 	u8			wlan_version[WCN36XX_HAL_VERSION_LENGTH + 1];
199 
200 	bool		first_boot;
201 
202 	/* IRQs */
203 	int			tx_irq;
204 	int			rx_irq;
205 	void __iomem		*ccu_base;
206 	void __iomem		*dxe_base;
207 
208 	struct rpmsg_endpoint	*smd_channel;
209 
210 	struct qcom_smem_state  *tx_enable_state;
211 	unsigned		tx_enable_state_bit;
212 	struct qcom_smem_state	*tx_rings_empty_state;
213 	unsigned		tx_rings_empty_state_bit;
214 
215 	/* prevents concurrent FW reconfiguration */
216 	struct mutex		conf_mutex;
217 
218 	/*
219 	 * smd_buf must be protected with smd_mutex to garantee
220 	 * that all messages are sent one after another
221 	 */
222 	u8			*hal_buf;
223 	size_t			hal_rsp_len;
224 	struct mutex		hal_mutex;
225 	struct completion	hal_rsp_compl;
226 	struct workqueue_struct	*hal_ind_wq;
227 	struct work_struct	hal_ind_work;
228 	spinlock_t		hal_ind_lock;
229 	struct list_head	hal_ind_queue;
230 
231 	struct cfg80211_scan_request *scan_req;
232 	bool			sw_scan;
233 	u8			sw_scan_opchannel;
234 	bool			sw_scan_init;
235 	u8			sw_scan_channel;
236 	struct ieee80211_vif	*sw_scan_vif;
237 	struct mutex		scan_lock;
238 	bool			scan_aborted;
239 
240 	/* DXE channels */
241 	struct wcn36xx_dxe_ch	dxe_tx_l_ch;	/* TX low */
242 	struct wcn36xx_dxe_ch	dxe_tx_h_ch;	/* TX high */
243 	struct wcn36xx_dxe_ch	dxe_rx_l_ch;	/* RX low */
244 	struct wcn36xx_dxe_ch	dxe_rx_h_ch;	/* RX high */
245 
246 	/* For synchronization of DXE resources from BH, IRQ and WQ contexts */
247 	spinlock_t	dxe_lock;
248 	bool                    queues_stopped;
249 
250 	/* Memory pools */
251 	struct wcn36xx_dxe_mem_pool mgmt_mem_pool;
252 	struct wcn36xx_dxe_mem_pool data_mem_pool;
253 
254 	struct sk_buff		*tx_ack_skb;
255 	struct timer_list	tx_ack_timer;
256 
257 	/* RF module */
258 	unsigned		rf_id;
259 
260 #ifdef CONFIG_WCN36XX_DEBUGFS
261 	/* Debug file system entry */
262 	struct wcn36xx_dfs_entry    dfs;
263 #endif /* CONFIG_WCN36XX_DEBUGFS */
264 
265 };
266 
wcn36xx_is_fw_version(struct wcn36xx * wcn,u8 major,u8 minor,u8 version,u8 revision)267 static inline bool wcn36xx_is_fw_version(struct wcn36xx *wcn,
268 					 u8 major,
269 					 u8 minor,
270 					 u8 version,
271 					 u8 revision)
272 {
273 	return (wcn->fw_major == major &&
274 		wcn->fw_minor == minor &&
275 		wcn->fw_version == version &&
276 		wcn->fw_revision == revision);
277 }
278 void wcn36xx_set_default_rates(struct wcn36xx_hal_supported_rates *rates);
279 void wcn36xx_set_default_rates_v1(struct wcn36xx_hal_supported_rates_v1 *rates);
280 
281 static inline
wcn36xx_priv_to_sta(struct wcn36xx_sta * sta_priv)282 struct ieee80211_sta *wcn36xx_priv_to_sta(struct wcn36xx_sta *sta_priv)
283 {
284 	return container_of((void *)sta_priv, struct ieee80211_sta, drv_priv);
285 }
286 
287 static inline
wcn36xx_vif_to_priv(struct ieee80211_vif * vif)288 struct wcn36xx_vif *wcn36xx_vif_to_priv(struct ieee80211_vif *vif)
289 {
290 	return (struct wcn36xx_vif *) vif->drv_priv;
291 }
292 
293 static inline
wcn36xx_priv_to_vif(struct wcn36xx_vif * vif_priv)294 struct ieee80211_vif *wcn36xx_priv_to_vif(struct wcn36xx_vif *vif_priv)
295 {
296 	return container_of((void *) vif_priv, struct ieee80211_vif, drv_priv);
297 }
298 
299 static inline
wcn36xx_sta_to_priv(struct ieee80211_sta * sta)300 struct wcn36xx_sta *wcn36xx_sta_to_priv(struct ieee80211_sta *sta)
301 {
302 	return (struct wcn36xx_sta *)sta->drv_priv;
303 }
304 
305 #endif	/* _WCN36XX_H_ */
306