Home
last modified time | relevance | path

Searched refs:WREG8 (Results 1 – 11 of 11) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/mgag200/
Dmgag200_drv.h37 #define WREG8(reg, v) iowrite8(v, ((void __iomem *)mdev->rmmio) + (reg)) macro
47 WREG8(MGA_MISC_OUT, v)
65 WREG8(ATTR_INDEX, reg); \
66 WREG8(ATTR_DATA, v); \
71 WREG8(MGAREG_SEQ_INDEX, reg); \
77 WREG8(MGAREG_SEQ_INDEX, reg); \
78 WREG8(MGAREG_SEQ_DATA, v); \
83 WREG8(MGAREG_CRTC_INDEX, reg); \
89 WREG8(MGAREG_CRTC_INDEX, reg); \
90 WREG8(MGAREG_CRTC_DATA, v); \
[all …]
Dmgag200_mode.c53 WREG8(DAC_INDEX + MGA1064_INDEX, 0); in mga_crtc_load_lut()
73 WREG8(DAC_INDEX + MGA1064_COL_PAL, r); in mga_crtc_load_lut()
74 WREG8(DAC_INDEX + MGA1064_COL_PAL, *g_ptr++ >> 8); in mga_crtc_load_lut()
75 WREG8(DAC_INDEX + MGA1064_COL_PAL, b); in mga_crtc_load_lut()
81 WREG8(DAC_INDEX + MGA1064_COL_PAL, *r_ptr++ >> 8); in mga_crtc_load_lut()
82 WREG8(DAC_INDEX + MGA1064_COL_PAL, *g_ptr++ >> 8); in mga_crtc_load_lut()
83 WREG8(DAC_INDEX + MGA1064_COL_PAL, *b_ptr++ >> 8); in mga_crtc_load_lut()
394 WREG8(MGAREG_CRTC_INDEX, 0x1e); in mga_g200wb_set_plls()
397 WREG8(MGAREG_CRTC_DATA, tmp+1); in mga_g200wb_set_plls()
401 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); in mga_g200wb_set_plls()
[all …]
Dmgag200_i2c.c38 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA); in mga_i2c_read_gpio()
46 WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL); in mga_i2c_set_gpio()
Dmgag200_mm.c102 WREG8(MGA_MISC_OUT, misc); in mgag200_mm_init()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
Dmxgpu_nv.c36 WREG8(NV_MAIBOX_CONTROL_RCV_OFFSET_BYTE, 2); in xgpu_nv_mailbox_send_ack()
41 WREG8(NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE, val ? 1 : 0); in xgpu_nv_mailbox_set_valid()
Dmxgpu_ai.c37 WREG8(AI_MAIBOX_CONTROL_RCV_OFFSET_BYTE, 2); in xgpu_ai_mailbox_send_ack()
42 WREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE, val ? 1 : 0); in xgpu_ai_mailbox_set_valid()
Damdgpu.h1067 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) macro
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
Dradeon_legacy_tv.c289 WREG8(RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_TEST_CNTL); in radeon_wait_pll_lock()
291 WREG8(RADEON_CLOCK_CNTL_DATA + 3, 0); in radeon_wait_pll_lock()
Dr100.c2886 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); in r100_pll_rreg()
2899 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); in r100_pll_wreg()
3790 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); in r100_mc_stop()
3821 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); in r100_mc_resume()
3834 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); in r100_vga_render_disable()
Dradeon_display.c75 WREG8(AVIVO_DC_LUT_RW_INDEX, 0); in avivo_crtc_load_lut()
212 WREG8(RADEON_PALETTE_INDEX, 0); in legacy_crtc_load_lut()
Dradeon.h2515 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) macro