| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/ |
| D | intel_timeline.c | 49 hwsp_alloc(struct intel_timeline *timeline, unsigned int *cacheline) in hwsp_alloc() argument
89 *cacheline = __ffs64(hwsp->free_bitmap); in hwsp_alloc()
90 hwsp->free_bitmap &= ~BIT_ULL(*cacheline); in hwsp_alloc()
100 static void __idle_hwsp_free(struct intel_timeline_hwsp *hwsp, int cacheline) in __idle_hwsp_free() argument
111 GEM_BUG_ON(cacheline >= BITS_PER_TYPE(hwsp->free_bitmap)); in __idle_hwsp_free()
112 hwsp->free_bitmap |= BIT_ULL(cacheline); in __idle_hwsp_free()
164 cacheline_alloc(struct intel_timeline_hwsp *hwsp, unsigned int cacheline) in cacheline_alloc() argument
169 GEM_BUG_ON(cacheline >= BIT(CACHELINE_BITS)); in cacheline_alloc()
182 cl->vaddr = page_pack_bits(vaddr, cacheline); in cacheline_alloc()
235 unsigned int cacheline; in intel_timeline_init() local
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| D | intel_ring.h | 110 #define cacheline(a) round_down(a, CACHELINE_BYTES) in assert_ring_tail_valid() macro
111 GEM_BUG_ON(cacheline(tail) == cacheline(head) && tail < head); in assert_ring_tail_valid()
112 #undef cacheline in assert_ring_tail_valid()
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| D | selftest_timeline.c | 72 unsigned long cacheline; in __mock_hwsp_timeline() local
79 cacheline = hwsp_cacheline(tl); in __mock_hwsp_timeline()
80 err = radix_tree_insert(&state->cachelines, cacheline, tl); in __mock_hwsp_timeline()
84 cacheline); in __mock_hwsp_timeline()
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| /kernel/linux/linux-5.10/tools/perf/Documentation/ |
| D | perf-c2c.txt | 20 you to track down the cacheline contentions.
82 Specify sorting fields for single cacheline display.
127 The perf c2c record command setup options related to HITM cacheline analysis
159 - sort all the data based on the cacheline address
160 - store access details for each cacheline
166 2) offsets details for each cacheline
168 For each cacheline in the 1) list we display following data:
172 - zero based index to identify the cacheline
175 - cacheline address (hex number)
178 - cacheline percentage of all Remote/Local HITM accesses
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| D | tips.txt | 37 To report cacheline events from previous recording: perf c2c report
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| /kernel/linux/linux-5.10/drivers/soc/qcom/ |
| D | smem.c | 153 __le32 cacheline; member
269 size_t cacheline[SMEM_HOST_COUNT]; member
287 size_t cacheline) in phdr_to_first_cached_entry() argument
292 return p + le32_to_cpu(phdr->size) - ALIGN(sizeof(*e), cacheline); in phdr_to_first_cached_entry()
321 cached_entry_next(struct smem_private_entry *e, size_t cacheline) in cached_entry_next() argument
325 return p - le32_to_cpu(e->size) - ALIGN(sizeof(*e), cacheline); in cached_entry_next()
513 size_t cacheline, in qcom_smem_get_private() argument
539 e = phdr_to_first_cached_entry(phdr, cacheline); in qcom_smem_get_private()
554 e = cached_entry_next(e, cacheline); in qcom_smem_get_private()
597 cacheln = __smem->cacheline[host]; in qcom_smem_get()
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| /kernel/linux/linux-5.10/include/asm-generic/ |
| D | vmlinux.lds.h | 1066 #define PERCPU_INPUT(cacheline) \ argument
1071 . = ALIGN(cacheline); \
1073 . = ALIGN(cacheline); \
1103 #define PERCPU_VADDR(cacheline, vaddr, phdr) \ argument
1106 PERCPU_INPUT(cacheline) \
1122 #define PERCPU_SECTION(cacheline) \ argument
1126 PERCPU_INPUT(cacheline) \
1148 #define RW_DATA(cacheline, pagealigned, inittask) \ argument
1154 CACHELINE_ALIGNED_DATA(cacheline) \
1155 READ_MOSTLY_DATA(cacheline) \
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| /kernel/linux/linux-5.10/drivers/md/bcache/ |
| D | bset.c | 526 unsigned int cacheline, in cacheline_to_bkey() argument
529 return ((void *) t->data) + cacheline * BSET_CACHELINE + offset * 8; in cacheline_to_bkey()
538 unsigned int cacheline, in bkey_to_cacheline_offset() argument
541 return (u64 *) k - (u64 *) cacheline_to_bkey(t, cacheline, 0); in bkey_to_cacheline_offset()
558 static struct bkey *table_to_bkey(struct bset_tree *t, unsigned int cacheline) in table_to_bkey() argument
560 return cacheline_to_bkey(t, cacheline, t->prev[cacheline]); in table_to_bkey()
694 unsigned int j, cacheline = 1; in bch_bset_build_written_tree() local
715 while (bkey_to_cacheline(t, k) < cacheline) in bch_bset_build_written_tree()
719 t->tree[j].m = bkey_to_cacheline_offset(t, cacheline++, k); in bch_bset_build_written_tree()
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| /kernel/linux/linux-5.10/drivers/lightnvm/ |
| D | pblk-rb.c | 140 entry->cacheline = pblk_cacheline_to_addr(init_entry++); in pblk_rb_init()
146 entry->cacheline = pblk_cacheline_to_addr(init_entry++); in pblk_rb_init()
260 entry->cacheline); in __pblk_rb_update_l2p()
353 pblk_update_map_cache(pblk, w_ctx.lba, entry->cacheline); in pblk_rb_write_entry_user()
377 if (!pblk_update_map_gc(pblk, w_ctx.lba, entry->cacheline, line, paddr)) in pblk_rb_write_entry_gc()
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| D | pblk-write.c | 166 if (!pblk_ppa_comp(ppa_l2p, entry->cacheline)) in pblk_prepare_resubmit()
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| D | pblk.h | 149 struct ppa_addr cacheline; /* Cacheline for this entry */ member
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| /kernel/linux/linux-5.10/scripts/gcc-plugins/ |
| D | Kconfig | 93 bool "Use cacheline-aware structure randomization"
98 best effort at restricting randomization to cacheline-sized
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| /kernel/linux/linux-5.10/kernel/ |
| D | Kconfig.hz | 14 contention and cacheline bounces as a result of timer interrupts.
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| /kernel/linux/linux-5.10/Documentation/sparc/ |
| D | adi.rst | 35 size is same as cacheline size which is 64 bytes. A task that sets ADI
103 the corresponding cacheline, a memory corruption trap occurs. By
123 the corresponding cacheline, a memory corruption trap occurs. If
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| /kernel/linux/linux-5.10/arch/sparc/kernel/ |
| D | prom_irqtrans.c | 355 static unsigned char cacheline[64] in tomatillo_wsync_handler() local
366 "i" (FPRS_FEF), "r" (&cacheline[0]), in tomatillo_wsync_handler()
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| D | cherrs.S | 203 sub %g1, %g2, %g1 ! Move down 1 cacheline
215 subcc %g1, %g2, %g1 ! Next cacheline
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| /kernel/linux/linux-5.10/arch/parisc/kernel/ |
| D | perf_asm.S | 132 ; Cacheline start (32-byte cacheline)
145 ; Cacheline start (32-byte cacheline)
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| /kernel/linux/linux-5.10/Documentation/locking/ |
| D | mutex-design.rst | 55 cacheline bouncing that common test-and-set spinlock implementations
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| /kernel/linux/linux-5.10/Documentation/driver-api/ |
| D | edac.rst | 46 lockstep is enabled, the cacheline is doubled, but it generally brings
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| /kernel/linux/linux-5.10/tools/perf/util/ |
| D | Build | 5 perf-y += cacheline.o
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| /kernel/linux/linux-5.10/Documentation/networking/device_drivers/ethernet/amazon/ |
| D | ena.rst | 28 and CPU cacheline optimized data placement.
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| /kernel/linux/linux-5.10/drivers/edac/ |
| D | Kconfig | 96 - inject_section (0..3, 16-byte section of 64-byte cacheline),
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| /kernel/linux/linux-5.10/Documentation/core-api/ |
| D | dma-api-howto.rst | 137 buffers were cacheline-aligned. Without that, you'd see cacheline
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| /kernel/linux/linux-5.10/drivers/char/ |
| D | Kconfig | 116 of threads across a large system which avoids bouncing a cacheline
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| /kernel/linux/linux-5.10/drivers/scsi/aic7xxx/ |
| D | aic7xxx.seq | 754 * We fetch a "cacheline aligned" and sized amount of data
758 * cacheline size is unknown.
795 * If the ending address is on a cacheline boundary,
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