Searched refs:cfgcr0 (Results 1 – 4 of 4) sorted by relevance
2325 val = pll->state.hw_state.cfgcr0; in cnl_ddi_pll_enable()2333 if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE) { in cnl_ddi_pll_enable()2443 hw_state->cfgcr0 = val; in cnl_ddi_pll_get_hw_state()2600 u32 cfgcr0, cfgcr1; in cnl_ddi_hdmi_pll_dividers() local2603 cfgcr0 = DPLL_CFGCR0_HDMI_MODE; in cnl_ddi_hdmi_pll_dividers()2608 cfgcr0 |= DPLL_CFGCR0_DCO_FRACTION(wrpll_params.dco_fraction) | in cnl_ddi_hdmi_pll_dividers()2620 crtc_state->dpll_hw_state.cfgcr0 = cfgcr0; in cnl_ddi_hdmi_pll_dividers()2680 dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * in __cnl_ddi_wrpll_get_freq()2683 dco_fraction = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >> in __cnl_ddi_wrpll_get_freq()2706 u32 cfgcr0; in cnl_ddi_dp_set_dpll_hw_state() local[all …]
191 u32 cfgcr0; member
942 seq_printf(m, " cfgcr0: 0x%08x\n", pll->state.hw_state.cfgcr0); in i915_shared_dplls_info()
13997 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); in intel_pipe_config_compare()