Searched refs:channel_width (Results 1 – 8 of 8) sorted by relevance
276 common->channel_width = BW_20MHZ; in rsi_set_default_parameters()403 if (common->channel_width == BW_40MHZ) { in rsi_load_radio_caps()428 common->channel_width == BW_20MHZ) in rsi_load_radio_caps()741 vap_caps->channel_bw = common->channel_width; in rsi_set_vap_capabilities()933 if (common->channel_width == BW_40MHZ) { in rsi_load_bootup_params()983 if (common->channel_width == BW_40MHZ) { in rsi_load_9116_bootup_params()1064 u8 prev_bw = common->channel_width; in rsi_band_check()1075 common->channel_width = BW_20MHZ; in rsi_band_check()1077 common->channel_width = BW_40MHZ; in rsi_band_check()1080 if (common->channel_width) in rsi_band_check()[all …]
262 u8 channel_width; member
405 u8 channel_width; member
248 mem_channel_width = vram_module->v9.channel_width; in amdgpu_atomfirmware_get_vram_info()268 mem_channel_width = vram_module->v10.channel_width; in amdgpu_atomfirmware_get_vram_info()288 mem_channel_width = vram_module->v11.channel_width; in amdgpu_atomfirmware_get_vram_info()
279 struct mvm_statistics_tx_channel_width channel_width; member285 struct mvm_statistics_tx_channel_width channel_width; member
1474 info->dram_channel_width_bytes = (1 << info_v23->vram_module[0].channel_width) / 8; in get_vram_info_v23()1493 info->dram_channel_width_bytes = (1 << info_v24->vram_module[0].channel_width) / 8; in get_vram_info_v24()1512 info->dram_channel_width_bytes = (1 << info_v25->vram_module[0].channel_width) / 8; in get_vram_info_v25()
2496 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT member2574 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT member2614 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT member
424 __field(u32, channel_width)465 __entry->channel_width = info->chandef.width;