Searched refs:clks_cfg (Results 1 – 12 of 12) sorted by relevance
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dml/ |
D | display_mode_lib.c | 137 display_clocks_and_cfg_st *clks_cfg; in dml_log_pipe_params() local 146 clks_cfg = &(pipes[i].clks_cfg); in dml_log_pipe_params() 244 dml_print("DML PARAMS: voltage = %d\n", clks_cfg->voltage); in dml_log_pipe_params() 245 dml_print("DML PARAMS: dppclk_mhz = %3.2f\n", clks_cfg->dppclk_mhz); in dml_log_pipe_params() 246 dml_print("DML PARAMS: refclk_mhz = %3.2f\n", clks_cfg->refclk_mhz); in dml_log_pipe_params() 247 dml_print("DML PARAMS: dispclk_mhz = %3.2f\n", clks_cfg->dispclk_mhz); in dml_log_pipe_params() 248 dml_print("DML PARAMS: dcfclk_mhz = %3.2f\n", clks_cfg->dcfclk_mhz); in dml_log_pipe_params() 249 dml_print("DML PARAMS: socclk_mhz = %3.2f\n", clks_cfg->socclk_mhz); in dml_log_pipe_params()
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D | display_mode_vba.c | 67 if (need_recalculate && pipes[0].clks_cfg.dppclk_mhz != 0) in dml_get_voltage_level() 387 display_clocks_and_cfg_st *clks = &pipes[j].clks_cfg; in fetch_pipe_params() 834 mode_lib->vba.VoltageLevel = mode_lib->vba.cache_pipes[0].clks_cfg.voltage; in ModeSupportAndSystemConfiguration() 844 mode_lib->vba.DCFCLK = mode_lib->vba.cache_pipes[0].clks_cfg.dcfclk_mhz; in ModeSupportAndSystemConfiguration() 845 mode_lib->vba.SOCCLK = mode_lib->vba.cache_pipes[0].clks_cfg.socclk_mhz; in ModeSupportAndSystemConfiguration() 846 if (mode_lib->vba.cache_pipes[0].clks_cfg.dispclk_mhz > 0.0) in ModeSupportAndSystemConfiguration() 847 mode_lib->vba.DISPCLK = mode_lib->vba.cache_pipes[0].clks_cfg.dispclk_mhz; in ModeSupportAndSystemConfiguration()
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D | display_mode_structs.h | 377 display_clocks_and_cfg_st clks_cfg; member
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D | dml1_display_rq_dlg_calc.c | 1018 double refclk_freq_in_mhz = e2e_pipe_param.clks_cfg.refclk_mhz; in dml1_rq_dlg_get_dlg_params() 1019 double dppclk_freq_in_mhz = e2e_pipe_param.clks_cfg.dppclk_mhz; in dml1_rq_dlg_get_dlg_params() 1020 double dispclk_freq_in_mhz = e2e_pipe_param.clks_cfg.dispclk_mhz; in dml1_rq_dlg_get_dlg_params()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/ |
D | dcn20_resource.c | 2052 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; 2968 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; 2969 …pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw… 2972 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 2981 pipes[pipe_cnt].clks_cfg.dppclk_mhz = 2991 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; 2992 pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; 2994 if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000) 2995 pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; 2996 if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000) [all …]
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/ |
D | dcn30_resource.c | 1623 …ation = dml->vba.WritebackAllowDRAMClockChangeEndPosition[j] * pipes[0].clks_cfg.refclk_mhz; /* nu… in dcn30_set_mcif_arb_params() 2219 pipes[0].clks_cfg.voltage = vlevel; in dcn30_calculate_wm_and_dlg() 2220 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn30_calculate_wm_and_dlg() 2221 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn30_calculate_wm_and_dlg() 2229 pipes[0].clks_cfg.voltage = 1; in dcn30_calculate_wm_and_dlg() 2230 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz; in dcn30_calculate_wm_and_dlg() 2245 pipes[0].clks_cfg.voltage = vlevel; in dcn30_calculate_wm_and_dlg() 2246 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn30_calculate_wm_and_dlg() 2338 …pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cn… in dcn30_calculate_wm_and_dlg() 2339 …pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn30_calculate_wm_and_dlg() [all …]
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn21/ |
D | dcn21_resource.c | 1037 pipes[0].clks_cfg.voltage = vlevel; in calculate_wm_set_for_vlevel() 1038 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel() 1039 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; in calculate_wm_set_for_vlevel() 1107 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; in dcn21_calculate_wm() 1108 …pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context… in dcn21_calculate_wm() 1111 pipes[pipe_cnt].clks_cfg.dppclk_mhz = in dcn21_calculate_wm() 1120 pipes[pipe_cnt].clks_cfg.dppclk_mhz = in dcn21_calculate_wm()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/calcs/ |
D | dcn_calcs.c | 491 input.clks_cfg.dcfclk_mhz = v->dcfclk; in dcn_bw_calc_rq_dlg_ttu() 492 input.clks_cfg.dispclk_mhz = v->dispclk; in dcn_bw_calc_rq_dlg_ttu() 493 input.clks_cfg.dppclk_mhz = v->dppclk; in dcn_bw_calc_rq_dlg_ttu() 494 input.clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; in dcn_bw_calc_rq_dlg_ttu() 495 input.clks_cfg.socclk_mhz = v->socclk; in dcn_bw_calc_rq_dlg_ttu() 496 input.clks_cfg.voltage = v->voltage_level; in dcn_bw_calc_rq_dlg_ttu()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
D | display_rq_dlg_calc_20v2.c | 798 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml20v2_rq_dlg_get_dlg_params()
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D | display_rq_dlg_calc_20.c | 798 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml20_rq_dlg_get_dlg_params()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
D | display_rq_dlg_calc_21.c | 844 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
D | display_rq_dlg_calc_30.c | 998 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params()
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