/kernel/linux/linux-5.10/sound/pci/echoaudio/ |
D | echoaudio_3g.c | 145 static u32 set_spdif_bits(struct echoaudio *chip, u32 control_reg, u32 rate) in set_spdif_bits() argument 147 control_reg &= E3G_SPDIF_FORMAT_CLEAR_MASK; in set_spdif_bits() 151 control_reg |= E3G_SPDIF_SAMPLE_RATE0 | E3G_SPDIF_SAMPLE_RATE1; in set_spdif_bits() 155 control_reg |= E3G_SPDIF_SAMPLE_RATE0; in set_spdif_bits() 158 control_reg |= E3G_SPDIF_SAMPLE_RATE1; in set_spdif_bits() 163 control_reg |= E3G_SPDIF_PRO_MODE; in set_spdif_bits() 166 control_reg |= E3G_SPDIF_NOT_AUDIO; in set_spdif_bits() 168 control_reg |= E3G_SPDIF_24_BIT | E3G_SPDIF_TWO_CHANNEL | in set_spdif_bits() 171 return control_reg; in set_spdif_bits() 179 u32 control_reg; in set_professional_spdif() local [all …]
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D | gina24_dsp.c | 124 u32 control_reg; in load_asic() local 154 control_reg = GML_CONVERTER_ENABLE | GML_48KHZ; in load_asic() 155 err = write_control_reg(chip, control_reg, true); in load_asic() 164 u32 control_reg, clock; in set_sample_rate() local 182 control_reg = le32_to_cpu(chip->comm_page->control_register); in set_sample_rate() 183 control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK; in set_sample_rate() 198 if (control_reg & GML_SPDIF_PRO_MODE) in set_sample_rate() 223 control_reg |= clock; in set_sample_rate() 229 return write_control_reg(chip, control_reg, false); in set_sample_rate() 236 u32 control_reg, clocks_from_dsp; in set_input_clock() local [all …]
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D | mona_dsp.c | 117 u32 control_reg; in load_asic() local 150 control_reg = GML_CONVERTER_ENABLE | GML_48KHZ; in load_asic() 151 err = write_control_reg(chip, control_reg, true); in load_asic() 198 u32 control_reg, clock; in set_sample_rate() local 244 control_reg = le32_to_cpu(chip->comm_page->control_register); in set_sample_rate() 245 control_reg &= GML_CLOCK_CLEAR_MASK; in set_sample_rate() 246 control_reg &= GML_SPDIF_RATE_CLEAR_MASK; in set_sample_rate() 261 if (control_reg & GML_SPDIF_PRO_MODE) in set_sample_rate() 286 control_reg |= clock; in set_sample_rate() 293 return write_control_reg(chip, control_reg, force_write); in set_sample_rate() [all …]
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D | layla24_dsp.c | 159 u32 control_reg, clock, base_rate; in set_sample_rate() local 176 control_reg = le32_to_cpu(chip->comm_page->control_register); in set_sample_rate() 177 control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK; in set_sample_rate() 194 if (control_reg & GML_SPDIF_PRO_MODE) in set_sample_rate() 219 control_reg |= GML_DOUBLE_SPEED_MODE; in set_sample_rate() 237 control_reg |= clock; in set_sample_rate() 242 "set_sample_rate: %d clock %d\n", rate, control_reg); in set_sample_rate() 244 return write_control_reg(chip, control_reg, false); in set_sample_rate() 251 u32 control_reg, clocks_from_dsp; in set_input_clock() local 254 control_reg = le32_to_cpu(chip->comm_page->control_register) & in set_input_clock() [all …]
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D | echoaudio_gml.c | 158 u32 control_reg; in set_professional_spdif() local 162 control_reg = le32_to_cpu(chip->comm_page->control_register); in set_professional_spdif() 163 control_reg &= GML_SPDIF_FORMAT_CLEAR_MASK; in set_professional_spdif() 166 control_reg |= GML_SPDIF_TWO_CHANNEL | GML_SPDIF_24_BIT | in set_professional_spdif() 170 control_reg |= GML_SPDIF_PRO_MODE; in set_professional_spdif() 174 control_reg |= GML_SPDIF_SAMPLE_RATE0 | in set_professional_spdif() 178 control_reg |= GML_SPDIF_SAMPLE_RATE0; in set_professional_spdif() 181 control_reg |= GML_SPDIF_SAMPLE_RATE1; in set_professional_spdif() 188 control_reg |= GML_SPDIF_SAMPLE_RATE0 | in set_professional_spdif() 192 control_reg |= GML_SPDIF_SAMPLE_RATE1; in set_professional_spdif() [all …]
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D | indigodj_dsp.c | 92 u32 control_reg; in set_sample_rate() local 96 control_reg = MIA_96000; in set_sample_rate() 99 control_reg = MIA_88200; in set_sample_rate() 102 control_reg = MIA_48000; in set_sample_rate() 105 control_reg = MIA_44100; in set_sample_rate() 108 control_reg = MIA_32000; in set_sample_rate() 117 if (control_reg != le32_to_cpu(chip->comm_page->control_register)) { in set_sample_rate() 122 chip->comm_page->control_register = cpu_to_le32(control_reg); in set_sample_rate()
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D | indigo_dsp.c | 92 u32 control_reg; in set_sample_rate() local 96 control_reg = MIA_96000; in set_sample_rate() 99 control_reg = MIA_88200; in set_sample_rate() 102 control_reg = MIA_48000; in set_sample_rate() 105 control_reg = MIA_44100; in set_sample_rate() 108 control_reg = MIA_32000; in set_sample_rate() 117 if (control_reg != le32_to_cpu(chip->comm_page->control_register)) { in set_sample_rate() 122 chip->comm_page->control_register = cpu_to_le32(control_reg); in set_sample_rate()
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D | mia_dsp.c | 109 u32 control_reg; in set_sample_rate() local 113 control_reg = MIA_96000; in set_sample_rate() 116 control_reg = MIA_88200; in set_sample_rate() 119 control_reg = MIA_48000; in set_sample_rate() 122 control_reg = MIA_44100; in set_sample_rate() 125 control_reg = MIA_32000; in set_sample_rate() 135 control_reg |= MIA_SPDIF; in set_sample_rate() 138 if (control_reg != le32_to_cpu(chip->comm_page->control_register)) { in set_sample_rate() 143 chip->comm_page->control_register = cpu_to_le32(control_reg); in set_sample_rate()
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D | indigo_express_dsp.c | 31 u32 clock, control_reg, old_control_reg; in set_sample_rate() local 37 control_reg = old_control_reg & ~INDIGO_EXPRESS_CLOCK_MASK; in set_sample_rate() 62 control_reg |= clock; in set_sample_rate() 63 if (control_reg != old_control_reg) { in set_sample_rate() 66 chip->comm_page->control_register = cpu_to_le32(control_reg); in set_sample_rate()
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D | echo3g_dsp.c | 120 u32 control_reg = le32_to_cpu(chip->comm_page->control_register); in set_phantom_power() local 123 control_reg |= E3G_PHANTOM_POWER; in set_phantom_power() 125 control_reg &= ~E3G_PHANTOM_POWER; in set_phantom_power() 128 return write_control_reg(chip, control_reg, in set_phantom_power()
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/kernel/linux/linux-5.10/drivers/scsi/pcmcia/ |
D | nsp_message.c | 15 unsigned char data_reg, control_reg; in nsp_message_in() local 33 control_reg = nsp_index_read(base, SCSIBUSCTRL); in nsp_message_in() 34 control_reg |= SCSI_ACK; in nsp_message_in() 35 nsp_index_write(base, SCSIBUSCTRL, control_reg); in nsp_message_in() 41 control_reg = nsp_index_read(base, SCSIBUSCTRL); in nsp_message_in() 42 control_reg &= ~SCSI_ACK; in nsp_message_in() 43 nsp_index_write(base, SCSIBUSCTRL, control_reg); in nsp_message_in()
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/kernel/linux/linux-5.10/drivers/clk/ |
D | clk-palmas.c | 35 unsigned int control_reg; member 67 cinfo->clk_desc->control_reg, in palmas_clks_prepare() 72 cinfo->clk_desc->control_reg, ret); in palmas_clks_prepare() 92 cinfo->clk_desc->control_reg, in palmas_clks_unprepare() 96 cinfo->clk_desc->control_reg, ret); in palmas_clks_unprepare() 109 cinfo->clk_desc->control_reg, &val); in palmas_clks_is_prepared() 112 cinfo->clk_desc->control_reg, ret); in palmas_clks_is_prepared() 138 .control_reg = PALMAS_CLK32KG_CTRL, 154 .control_reg = PALMAS_CLK32KGAUDIO_CTRL, 211 cinfo->clk_desc->control_reg, in palmas_clks_init_configure() [all …]
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/kernel/linux/linux-5.10/drivers/clk/ti/ |
D | apll.c | 63 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in dra7_apll_enable() 66 ti_clk_ll_ops->clk_writel(v, &ad->control_reg); in dra7_apll_enable() 102 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in dra7_apll_disable() 105 ti_clk_ll_ops->clk_writel(v, &ad->control_reg); in dra7_apll_disable() 116 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in dra7_apll_is_enabled() 218 ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg); in of_dra7_apll_setup() 247 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in omap2_apll_is_enabled() 273 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in omap2_apll_enable() 276 ti_clk_ll_ops->clk_writel(v, &ad->control_reg); in omap2_apll_enable() 303 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in omap2_apll_disable() [all …]
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D | dpll3xxx.c | 54 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in _omap3_dpll_write_clken() 57 ti_clk_ll_ops->clk_writel(v, &dd->control_reg); in _omap3_dpll_write_clken() 317 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap3_noncore_dpll_program() 320 ti_clk_ll_ops->clk_writel(v, &dd->control_reg); in omap3_noncore_dpll_program() 374 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap3_noncore_dpll_program() 390 ti_clk_ll_ops->clk_writel(v, &dd->control_reg); in omap3_noncore_dpll_program() 773 v = ti_clk_ll_ops->clk_readl(&dd->control_reg) & dd->enable_mask; in omap3_clkoutx2_recalc() 797 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap3_core_dpll_save_context() 858 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap3_noncore_dpll_save_context() 887 ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap3_noncore_dpll_restore_context()
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D | clkt_dpll.c | 213 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap2_init_dpll_parent() 249 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap2_get_dpll_rate()
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/kernel/linux/linux-5.10/drivers/watchdog/ |
D | ts72xx_wdt.c | 45 void __iomem *control_reg; member 56 writeb(priv->regval, priv->control_reg); in ts72xx_wdt_start() 66 writeb(TS72XX_WDT_CTRL_DISABLE, priv->control_reg); in ts72xx_wdt_stop() 134 priv->control_reg = devm_platform_ioremap_resource(pdev, 0); in ts72xx_wdt_probe() 135 if (IS_ERR(priv->control_reg)) in ts72xx_wdt_probe() 136 return PTR_ERR(priv->control_reg); in ts72xx_wdt_probe()
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/kernel/linux/linux-5.10/arch/mips/cavium-octeon/executive/ |
D | cvmx-helper-sgmii.c | 139 union cvmx_pcsx_mrx_control_reg control_reg; in __cvmx_helper_sgmii_hardware_init_link() local 149 control_reg.u64 = in __cvmx_helper_sgmii_hardware_init_link() 152 control_reg.s.reset = 1; in __cvmx_helper_sgmii_hardware_init_link() 154 control_reg.u64); in __cvmx_helper_sgmii_hardware_init_link() 169 control_reg.s.rst_an = 1; in __cvmx_helper_sgmii_hardware_init_link() 170 control_reg.s.an_en = 1; in __cvmx_helper_sgmii_hardware_init_link() 171 control_reg.s.pwr_dn = 0; in __cvmx_helper_sgmii_hardware_init_link() 173 control_reg.u64); in __cvmx_helper_sgmii_hardware_init_link()
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/kernel/linux/linux-5.10/drivers/tty/serial/ |
D | pmac_zilog.h | 55 volatile u8 __iomem *control_reg; member 88 writeb(reg, port->control_reg); in read_zsreg() 89 return readb(port->control_reg); in read_zsreg() 95 writeb(reg, port->control_reg); in write_zsreg() 96 writeb(value, port->control_reg); in write_zsreg() 111 (void)readb(port->control_reg); in zssync()
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/kernel/linux/linux-5.10/drivers/power/supply/ |
D | ds2781_battery.c | 359 u8 *control_reg) in ds2781_get_control_register() argument 361 return ds2781_read8(dev_info, control_reg, DS2781_CONTROL); in ds2781_get_control_register() 365 u8 control_reg) in ds2781_set_control_register() argument 369 ret = ds2781_write(dev_info, &control_reg, in ds2781_set_control_register() 450 u8 control_reg; in ds2781_get_pmod_enabled() local 455 ret = ds2781_get_control_register(dev_info, &control_reg); in ds2781_get_pmod_enabled() 460 !!(control_reg & DS2781_CONTROL_PMOD)); in ds2781_get_pmod_enabled() 469 u8 control_reg, new_setting; in ds2781_set_pmod_enabled() local 474 ret = ds2781_get_control_register(dev_info, &control_reg); in ds2781_set_pmod_enabled() 488 control_reg |= DS2781_CONTROL_PMOD; in ds2781_set_pmod_enabled() [all …]
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D | ds2780_battery.c | 357 u8 *control_reg) in ds2780_get_control_register() argument 359 return ds2780_read8(dev_info, control_reg, DS2780_CONTROL_REG); in ds2780_get_control_register() 363 u8 control_reg) in ds2780_set_control_register() argument 367 ret = ds2780_write(dev_info, &control_reg, in ds2780_set_control_register() 448 u8 control_reg; in ds2780_get_pmod_enabled() local 453 ret = ds2780_get_control_register(dev_info, &control_reg); in ds2780_get_pmod_enabled() 458 !!(control_reg & DS2780_CONTROL_REG_PMOD)); in ds2780_get_pmod_enabled() 467 u8 control_reg, new_setting; in ds2780_set_pmod_enabled() local 472 ret = ds2780_get_control_register(dev_info, &control_reg); in ds2780_set_pmod_enabled() 486 control_reg |= DS2780_CONTROL_REG_PMOD; in ds2780_set_pmod_enabled() [all …]
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/kernel/linux/linux-5.10/drivers/regulator/ |
D | as3722-regulator.c | 55 u32 control_reg; member 85 .control_reg = AS3722_SD0_CONTROL_REG, 97 .control_reg = AS3722_SD1_CONTROL_REG, 110 .control_reg = AS3722_SD23_CONTROL_REG, 124 .control_reg = AS3722_SD23_CONTROL_REG, 138 .control_reg = AS3722_SD4_CONTROL_REG, 152 .control_reg = AS3722_SD5_CONTROL_REG, 165 .control_reg = AS3722_SD6_CONTROL_REG, 427 if (!as3722_reg_lookup[id].control_reg) in as3722_sd_get_mode() 430 ret = as3722_read(as3722, as3722_reg_lookup[id].control_reg, &val); in as3722_sd_get_mode() [all …]
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D | anatop-regulator.c | 166 u32 control_reg; in anatop_regulator_probe() local 203 ret = of_property_read_u32(np, "anatop-reg-offset", &control_reg); in anatop_regulator_probe() 247 rdesc->vsel_reg = control_reg; in anatop_regulator_probe() 258 if (control_reg && sreg->delay_bit_width) { in anatop_regulator_probe() 300 rdesc->enable_reg = control_reg; in anatop_regulator_probe()
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D | ti-abb-regulator.c | 105 void __iomem *control_reg; member 270 ti_abb_rmw(regs->opp_sel_mask, info->opp_sel, abb->control_reg); in ti_abb_set_opp() 281 ti_abb_rmw(regs->opp_change_mask, 1, abb->control_reg); in ti_abb_set_opp() 735 abb->control_reg = abb->base + abb->regs->control_off; in ti_abb_probe() 740 abb->control_reg = devm_ioremap_resource(dev, res); in ti_abb_probe() 741 if (IS_ERR(abb->control_reg)) in ti_abb_probe() 742 return PTR_ERR(abb->control_reg); in ti_abb_probe()
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/kernel/linux/linux-5.10/drivers/staging/fieldbus/anybuss/ |
D | arcx-anybus.c | 45 u8 control_reg; member 58 cd->control_reg &= ~rst_bit; in do_reset() 60 cd->control_reg |= rst_bit; in do_reset() 61 writeb(cd->control_reg, cd->cpld_base + CPLD_CONTROL); in do_reset()
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/kernel/linux/linux-5.10/drivers/i2c/busses/ |
D | i2c-mt65xx.c | 482 u16 control_reg; in mtk_i2c_init_hw() local 560 control_reg = I2C_CONTROL_ACKERR_DET_EN | in mtk_i2c_init_hw() 563 control_reg |= I2C_CONTROL_DMAACK_EN | I2C_CONTROL_ASYNC_MODE; in mtk_i2c_init_hw() 565 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); in mtk_i2c_init_hw() 848 u16 control_reg; in mtk_i2c_do_transfer() local 865 control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) & in mtk_i2c_do_transfer() 868 control_reg |= I2C_CONTROL_RS; in mtk_i2c_do_transfer() 871 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS; in mtk_i2c_do_transfer() 873 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); in mtk_i2c_do_transfer()
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