| /kernel/linux/linux-5.10/drivers/isdn/capi/ |
| D | kcapi.c | 66 capi_ctr_get(struct capi_ctr *ctr) in capi_ctr_get() argument
68 if (!try_module_get(ctr->owner)) in capi_ctr_get()
70 return ctr; in capi_ctr_get()
74 capi_ctr_put(struct capi_ctr *ctr) in capi_ctr_put() argument
76 module_put(ctr->owner); in capi_ctr_put()
147 register_appl(struct capi_ctr *ctr, u16 applid, capi_register_params *rparam) in register_appl() argument
149 ctr = capi_ctr_get(ctr); in register_appl()
151 if (ctr) in register_appl()
152 ctr->register_appl(ctr, applid, rparam); in register_appl()
159 static void release_appl(struct capi_ctr *ctr, u16 applid) in release_appl() argument
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| D | kcapi_proc.c | 66 struct capi_ctr *ctr = *(struct capi_ctr **) v; in controller_show() local
68 if (!ctr) in controller_show()
72 ctr->cnr, ctr->driver_name, in controller_show()
73 state2str(ctr->state), in controller_show()
74 ctr->name, in controller_show()
75 ctr->procinfo ? ctr->procinfo(ctr) : ""); in controller_show()
82 struct capi_ctr *ctr = *(struct capi_ctr **) v; in contrstats_show() local
84 if (!ctr) in contrstats_show()
88 ctr->cnr, in contrstats_show()
89 ctr->nrecvctlpkt, in contrstats_show()
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| /kernel/linux/linux-5.10/drivers/media/platform/qcom/venus/ |
| D | venc_ctrls.c | 72 struct venc_controls *ctr = &inst->controls.enc; in venc_op_s_ctrl() local
81 ctr->bitrate_mode = ctrl->val; in venc_op_s_ctrl()
84 ctr->bitrate = ctrl->val; in venc_op_s_ctrl()
88 brate.bitrate = ctr->bitrate; in venc_op_s_ctrl()
100 ctr->bitrate_peak = ctrl->val; in venc_op_s_ctrl()
103 ctr->h264_entropy_mode = ctrl->val; in venc_op_s_ctrl()
106 ctr->profile.mpeg4 = ctrl->val; in venc_op_s_ctrl()
109 ctr->profile.h264 = ctrl->val; in venc_op_s_ctrl()
112 ctr->profile.hevc = ctrl->val; in venc_op_s_ctrl()
115 ctr->profile.vp8 = ctrl->val; in venc_op_s_ctrl()
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| D | vdec_ctrls.c | 16 struct vdec_controls *ctr = &inst->controls.dec; in vdec_op_s_ctrl() local
20 ctr->post_loop_deb_mode = ctrl->val; in vdec_op_s_ctrl()
26 ctr->profile = ctrl->val; in vdec_op_s_ctrl()
31 ctr->level = ctrl->val; in vdec_op_s_ctrl()
43 struct vdec_controls *ctr = &inst->controls.dec; in vdec_op_g_volatile_ctrl() local
56 ctr->profile = profile; in vdec_op_g_volatile_ctrl()
57 ctrl->val = ctr->profile; in vdec_op_g_volatile_ctrl()
64 ctr->level = level; in vdec_op_g_volatile_ctrl()
65 ctrl->val = ctr->level; in vdec_op_g_volatile_ctrl()
68 ctrl->val = ctr->post_loop_deb_mode; in vdec_op_g_volatile_ctrl()
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| /kernel/linux/linux-5.10/arch/powerpc/oprofile/ |
| D | op_model_fsl_emb.c | 27 static inline u32 get_pmlca(int ctr) in get_pmlca() argument
31 switch (ctr) { in get_pmlca()
57 static inline void set_pmlca(int ctr, u32 pmlca) in set_pmlca() argument
59 switch (ctr) { in set_pmlca()
130 static void init_pmc_stop(int ctr) in init_pmc_stop() argument
136 switch (ctr) { in init_pmc_stop()
166 static void set_pmc_event(int ctr, int event) in set_pmc_event() argument
170 pmlca = get_pmlca(ctr); in set_pmc_event()
176 set_pmlca(ctr, pmlca); in set_pmc_event()
179 static void set_pmc_user_kernel(int ctr, int user, int kernel) in set_pmc_user_kernel() argument
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| D | op_model_cell.c | 282 static void set_pm_event(u32 ctr, int event, u32 unit_mask) in set_pm_event() argument
291 pm_regs.pm07_cntrl[ctr] = CBE_COUNT_ALL_CYCLES; in set_pm_event()
292 p = &(pm_signal[ctr]); in set_pm_event()
299 pm_regs.pm07_cntrl[ctr] = 0; in set_pm_event()
309 p = &(pm_signal[ctr]); in set_pm_event()
315 pm_regs.pm07_cntrl[ctr] = 0; in set_pm_event()
316 pm_regs.pm07_cntrl[ctr] |= PM07_CTR_COUNT_CYCLES(count_cycles); in set_pm_event()
317 pm_regs.pm07_cntrl[ctr] |= PM07_CTR_POLARITY(polarity); in set_pm_event()
318 pm_regs.pm07_cntrl[ctr] |= PM07_CTR_INPUT_CONTROL(input_control); in set_pm_event()
343 pm_regs.pm07_cntrl[ctr] |= PM07_CTR_INPUT_MUX(signal_bit); in set_pm_event()
[all …]
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| D | op_model_7450.c | 78 static int fsl7450_cpu_setup(struct op_counter_config *ctr) in fsl7450_cpu_setup() argument
92 static int fsl7450_reg_setup(struct op_counter_config *ctr, in fsl7450_reg_setup() argument
105 reset_value[i] = 0x80000000UL - ctr[i].count; in fsl7450_reg_setup()
108 mmcr0_val = MMCR0_INIT | mmcr0_event1(ctr[0].event) in fsl7450_reg_setup()
109 | mmcr0_event2(ctr[1].event); in fsl7450_reg_setup()
119 mmcr1_val = mmcr1_event3(ctr[2].event) in fsl7450_reg_setup()
120 | mmcr1_event4(ctr[3].event); in fsl7450_reg_setup()
122 mmcr1_val |= mmcr1_event5(ctr[4].event) in fsl7450_reg_setup()
123 | mmcr1_event6(ctr[5].event); in fsl7450_reg_setup()
131 static int fsl7450_start(struct op_counter_config *ctr) in fsl7450_start() argument
[all …]
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| D | common.c | 24 static struct op_counter_config ctr[OP_MAX_COUNTER]; variable
31 model->handle_interrupt(regs, ctr); in op_handle_interrupt()
38 ret = model->cpu_setup(ctr); in op_powerpc_cpu_setup()
56 op_per_cpu_rc = model->reg_setup(ctr, &sys, model->num_counters); in op_powerpc_setup()
86 ret = model->start(ctr); in op_powerpc_cpu_start()
96 return model->global_start(ctr); in op_powerpc_start()
161 oprofilefs_create_ulong(dir, "enabled", &ctr[i].enabled); in op_powerpc_create_files()
162 oprofilefs_create_ulong(dir, "event", &ctr[i].event); in op_powerpc_create_files()
163 oprofilefs_create_ulong(dir, "count", &ctr[i].count); in op_powerpc_create_files()
172 oprofilefs_create_ulong(dir, "kernel", &ctr[i].kernel); in op_powerpc_create_files()
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| D | op_model_pa6t.c | 79 static int pa6t_reg_setup(struct op_counter_config *ctr, in pa6t_reg_setup() argument
93 if (!ctr[pmc].enabled) { in pa6t_reg_setup()
121 reset_value[pmc] = (0x1UL << 39) - ctr[pmc].count; in pa6t_reg_setup()
130 static int pa6t_cpu_setup(struct op_counter_config *ctr) in pa6t_cpu_setup() argument
150 static int pa6t_start(struct op_counter_config *ctr) in pa6t_start() argument
158 if (ctr[i].enabled) in pa6t_start()
188 struct op_counter_config *ctr) in pa6t_handle_interrupt() argument
206 if (oprofile_running && ctr[i].enabled) { in pa6t_handle_interrupt()
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| /kernel/linux/linux-5.10/arch/alpha/oprofile/ |
| D | op_model_ev4.c | 21 struct op_counter_config *ctr, in ev4_reg_setup() argument
39 ctl |= (ctr[0].enabled ? ctr[0].event << 8 : 14 << 8); in ev4_reg_setup()
40 ctl |= (ctr[1].enabled ? (ctr[1].event - 16) << 32 : 7ul << 32); in ev4_reg_setup()
48 count = ctr[0].count; in ev4_reg_setup()
53 ctr[0].count = count; in ev4_reg_setup()
54 ctl |= (ctr[0].enabled && hilo) << 3; in ev4_reg_setup()
56 count = ctr[1].count; in ev4_reg_setup()
61 ctr[1].count = count; in ev4_reg_setup()
62 ctl |= (ctr[1].enabled && hilo); in ev4_reg_setup()
94 struct op_counter_config *ctr) in ev4_handle_interrupt() argument
[all …]
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| D | op_model_ev67.c | 22 struct op_counter_config *ctr, in ev67_reg_setup() argument
32 if (ctr[1].enabled) { in ev67_reg_setup()
33 ctl |= (ctr[1].event & 3) << 2; in ev67_reg_setup()
35 if (ctr[0].event == 0) /* cycles */ in ev67_reg_setup()
52 unsigned long count = ctr[i].count; in ev67_reg_setup()
53 if (!ctr[i].enabled) in ev67_reg_setup()
58 ctr[i].count = count; in ev67_reg_setup()
84 ev67_reset_ctr(struct op_register_config *reg, unsigned long ctr) in ev67_reset_ctr() argument
86 wrperfmon(6, reg->reset_values | (1 << ctr)); in ev67_reset_ctr()
133 struct op_counter_config *ctr, unsigned long event) in op_add_pm() argument
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| D | op_model_ev6.c | 21 struct op_counter_config *ctr, in ev6_reg_setup() argument
29 if (ctr[0].enabled && ctr[0].event) in ev6_reg_setup()
30 ctl |= (ctr[0].event & 1) << 4; in ev6_reg_setup()
31 if (ctr[1].enabled) in ev6_reg_setup()
32 ctl |= (ctr[1].event - 2) & 15; in ev6_reg_setup()
47 unsigned long count = ctr[i].count; in ev6_reg_setup()
48 if (!ctr[i].enabled) in ev6_reg_setup()
53 ctr[i].count = count; in ev6_reg_setup()
79 ev6_reset_ctr(struct op_register_config *reg, unsigned long ctr) in ev6_reset_ctr() argument
81 wrperfmon(6, reg->reset_values | (1 << ctr)); in ev6_reset_ctr()
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| D | op_model_ev5.c | 26 struct op_counter_config *ctr, in common_reg_setup() argument
47 unsigned long event = ctr[i].event; in common_reg_setup()
48 if (!ctr[i].enabled) in common_reg_setup()
91 unsigned long max, hilo, count = ctr[i].count; in common_reg_setup()
92 if (!ctr[i].enabled) in common_reg_setup()
103 ctr[i].count = count; in common_reg_setup()
117 struct op_counter_config *ctr, in ev5_reg_setup() argument
120 common_reg_setup(reg, ctr, sys, 19, 22); in ev5_reg_setup()
125 struct op_counter_config *ctr, in pca56_reg_setup() argument
128 common_reg_setup(reg, ctr, sys, 8, 11); in pca56_reg_setup()
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| D | common.c | 30 static struct op_counter_config ctr[20]; variable
39 model->handle_interrupt(which, regs, ctr); in op_handle_interrupt()
60 if (ctr[i].enabled) in op_axp_setup()
65 model->reg_setup(®, ctr, &sys); in op_axp_setup()
120 oprofilefs_create_ulong(dir, "enabled", &ctr[i].enabled); in op_axp_create_files()
121 oprofilefs_create_ulong(dir, "event", &ctr[i].event); in op_axp_create_files()
122 oprofilefs_create_ulong(dir, "count", &ctr[i].count); in op_axp_create_files()
124 oprofilefs_create_ulong(dir, "kernel", &ctr[i].kernel); in op_axp_create_files()
125 oprofilefs_create_ulong(dir, "user", &ctr[i].user); in op_axp_create_files()
126 oprofilefs_create_ulong(dir, "unit_mask", &ctr[i].unit_mask); in op_axp_create_files()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/pm/ |
| D | nv40.c | 28 struct nvkm_perfctr *ctr) in nv40_perfctr_init() argument
31 u32 log = ctr->logic_op; in nv40_perfctr_init()
36 src |= ctr->signal[i] << (i * 8); in nv40_perfctr_init()
39 nvkm_wr32(device, 0x00a400 + dom->addr + (ctr->slot * 0x40), src); in nv40_perfctr_init()
40 nvkm_wr32(device, 0x00a420 + dom->addr + (ctr->slot * 0x40), log); in nv40_perfctr_init()
45 struct nvkm_perfctr *ctr) in nv40_perfctr_read() argument
49 switch (ctr->slot) { in nv40_perfctr_read()
50 case 0: ctr->ctr = nvkm_rd32(device, 0x00a700 + dom->addr); break; in nv40_perfctr_read()
51 case 1: ctr->ctr = nvkm_rd32(device, 0x00a6c0 + dom->addr); break; in nv40_perfctr_read()
52 case 2: ctr->ctr = nvkm_rd32(device, 0x00a680 + dom->addr); break; in nv40_perfctr_read()
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| D | gf100.c | 129 struct nvkm_perfctr *ctr) in gf100_perfctr_init() argument
132 u32 log = ctr->logic_op; in gf100_perfctr_init()
137 src |= ctr->signal[i] << (i * 8); in gf100_perfctr_init()
141 nvkm_wr32(device, dom->addr + 0x040 + (ctr->slot * 0x08), src); in gf100_perfctr_init()
142 nvkm_wr32(device, dom->addr + 0x044 + (ctr->slot * 0x08), log); in gf100_perfctr_init()
147 struct nvkm_perfctr *ctr) in gf100_perfctr_read() argument
151 switch (ctr->slot) { in gf100_perfctr_read()
152 case 0: ctr->ctr = nvkm_rd32(device, dom->addr + 0x08c); break; in gf100_perfctr_read()
153 case 1: ctr->ctr = nvkm_rd32(device, dom->addr + 0x088); break; in gf100_perfctr_read()
154 case 2: ctr->ctr = nvkm_rd32(device, dom->addr + 0x080); break; in gf100_perfctr_read()
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| D | base.c | 129 nvkm_perfsrc_enable(struct nvkm_pm *pm, struct nvkm_perfctr *ctr) in nvkm_perfsrc_enable() argument
140 for (j = 0; j < 8 && ctr->source[i][j]; j++) { in nvkm_perfsrc_enable()
141 sig = nvkm_perfsig_find(pm, ctr->domain, in nvkm_perfsrc_enable()
142 ctr->signal[i], &dom); in nvkm_perfsrc_enable()
146 src = nvkm_perfsrc_find(pm, sig, ctr->source[i][j]); in nvkm_perfsrc_enable()
155 value |= ((ctr->source[i][j] >> 32) << src->shift); in nvkm_perfsrc_enable()
168 nvkm_perfsrc_disable(struct nvkm_pm *pm, struct nvkm_perfctr *ctr) in nvkm_perfsrc_disable() argument
179 for (j = 0; j < 8 && ctr->source[i][j]; j++) { in nvkm_perfsrc_disable()
180 sig = nvkm_perfsig_find(pm, ctr->domain, in nvkm_perfsrc_disable()
181 ctr->signal[i], &dom); in nvkm_perfsrc_disable()
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| /kernel/linux/linux-5.10/arch/mips/oprofile/ |
| D | op_model_loongson3.c | 62 static void loongson3_reg_setup(struct op_counter_config *ctr) in loongson3_reg_setup() argument
71 if (ctr[0].enabled) { in loongson3_reg_setup()
72 control1 |= LOONGSON3_PERFCTRL_EVENT(0, ctr[0].event) | in loongson3_reg_setup()
74 if (ctr[0].kernel) in loongson3_reg_setup()
76 if (ctr[0].user) in loongson3_reg_setup()
78 reg.reset_counter1 = 0x8000000000000000ULL - ctr[0].count; in loongson3_reg_setup()
81 if (ctr[1].enabled) { in loongson3_reg_setup()
82 control2 |= LOONGSON3_PERFCTRL_EVENT(1, ctr[1].event) | in loongson3_reg_setup()
84 if (ctr[1].kernel) in loongson3_reg_setup()
86 if (ctr[1].user) in loongson3_reg_setup()
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| D | common.c | 25 static struct op_counter_config ctr[20]; variable
30 model->reg_setup(ctr); in op_mips_setup()
49 oprofilefs_create_ulong(dir, "enabled", &ctr[i].enabled); in op_mips_create_files()
50 oprofilefs_create_ulong(dir, "event", &ctr[i].event); in op_mips_create_files()
51 oprofilefs_create_ulong(dir, "count", &ctr[i].count); in op_mips_create_files()
52 oprofilefs_create_ulong(dir, "kernel", &ctr[i].kernel); in op_mips_create_files()
53 oprofilefs_create_ulong(dir, "user", &ctr[i].user); in op_mips_create_files()
54 oprofilefs_create_ulong(dir, "exl", &ctr[i].exl); in op_mips_create_files()
56 oprofilefs_create_ulong(dir, "unit_mask", &ctr[i].unit_mask); in op_mips_create_files()
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| /kernel/linux/linux-5.10/drivers/parport/ |
| D | parport_gsc.h | 53 unsigned char ctr; member
95 unsigned char ctr = priv->ctr; in __parport_gsc_frob_control() local
99 ctr, ((ctr & ~mask) ^ val) & priv->ctr_writable); in __parport_gsc_frob_control()
101 ctr = (ctr & ~mask) ^ val; in __parport_gsc_frob_control()
102 ctr &= priv->ctr_writable; /* only write writable bits. */ in __parport_gsc_frob_control()
103 parport_writeb (ctr, CONTROL (p)); in __parport_gsc_frob_control()
104 priv->ctr = ctr; /* Update soft copy */ in __parport_gsc_frob_control()
105 return ctr; in __parport_gsc_frob_control()
143 return priv->ctr & rm; /* Use soft copy */ in parport_gsc_read_control()
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| /kernel/linux/linux-5.10/net/rds/ |
| D | stats.c | 87 struct rds_info_counter ctr; in rds_stats_info_copy() local
91 BUG_ON(strlen(names[i]) >= sizeof(ctr.name)); in rds_stats_info_copy()
92 strncpy(ctr.name, names[i], sizeof(ctr.name) - 1); in rds_stats_info_copy()
93 ctr.name[sizeof(ctr.name) - 1] = '\0'; in rds_stats_info_copy()
94 ctr.value = values[i]; in rds_stats_info_copy()
96 rds_info_copy(iter, &ctr, sizeof(ctr)); in rds_stats_info_copy()
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| /kernel/linux/linux-5.10/include/linux/ |
| D | parport_pc.h | 21 unsigned char ctr; member
100 dcr = i ? priv->ctr : inb (CONTROL (p)); in dump_parport_state()
133 unsigned char ctr = priv->ctr; in __parport_pc_frob_control() local
137 mask, val, ctr, ((ctr & ~mask) ^ val) & priv->ctr_writable); in __parport_pc_frob_control()
139 ctr = (ctr & ~mask) ^ val; in __parport_pc_frob_control()
140 ctr &= priv->ctr_writable; /* only write writable bits. */ in __parport_pc_frob_control()
141 outb (ctr, CONTROL (p)); in __parport_pc_frob_control()
142 priv->ctr = ctr; /* Update soft copy */ in __parport_pc_frob_control()
143 return ctr; in __parport_pc_frob_control()
181 return priv->ctr & rm; /* Use soft copy */ in parport_pc_read_control()
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| /kernel/linux/linux-5.10/arch/powerpc/include/asm/ |
| D | cell-pmu.h | 22 #define CBE_PM_16BIT_CTR(ctr) (1 << (24 - ((ctr) & (NR_PHYS_CTRS - 1)))) argument
52 #define CBE_PM_CTR_OVERFLOW_INTR(ctr) (1 << (31 - ((ctr) & 7))) argument
68 extern u32 cbe_read_ctr(u32 cpu, u32 ctr);
69 extern void cbe_write_ctr(u32 cpu, u32 ctr, u32 val);
71 extern u32 cbe_read_pm07_control(u32 cpu, u32 ctr);
72 extern void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val);
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| /kernel/linux/linux-5.10/arch/arm64/include/asm/ |
| D | cache.h | 24 #define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK) argument
112 u32 ctr = read_cpuid_cachetype(); in read_cpuid_effective_cachetype() local
114 if (!(ctr & BIT(CTR_IDC_SHIFT))) { in read_cpuid_effective_cachetype()
119 ctr |= BIT(CTR_IDC_SHIFT); in read_cpuid_effective_cachetype()
122 return ctr; in read_cpuid_effective_cachetype()
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| /kernel/linux/linux-5.10/arch/powerpc/platforms/cell/ |
| D | pmu.c | 113 u32 cbe_read_ctr(u32 cpu, u32 ctr) in cbe_read_ctr() argument
116 u32 phys_ctr = ctr & (NR_PHYS_CTRS - 1); in cbe_read_ctr()
121 val = (ctr < NR_PHYS_CTRS) ? (val >> 16) : (val & 0xffff); in cbe_read_ctr()
127 void cbe_write_ctr(u32 cpu, u32 ctr, u32 val) in cbe_write_ctr() argument
132 phys_ctr = ctr & (NR_PHYS_CTRS - 1); in cbe_write_ctr()
137 if (ctr < NR_PHYS_CTRS) in cbe_write_ctr()
152 u32 cbe_read_pm07_control(u32 cpu, u32 ctr) in cbe_read_pm07_control() argument
156 if (ctr < NR_CTRS) in cbe_read_pm07_control()
157 READ_SHADOW_REG(pm07_control, pm07_control[ctr]); in cbe_read_pm07_control()
163 void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val) in cbe_write_pm07_control() argument
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