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Searched refs:div_base (Results 1 – 6 of 6) sorted by relevance

/kernel/linux/linux-5.10/drivers/clk/bcm/
Dclk-iproc-asiu.c37 void __iomem *div_base; member
92 val = readl(asiu->div_base + clk->div.offset); in iproc_asiu_clk_recalc_rate()
142 val = readl(asiu->div_base + clk->div.offset); in iproc_asiu_clk_set_rate()
144 writel(val, asiu->div_base + clk->div.offset); in iproc_asiu_clk_set_rate()
156 val = readl(asiu->div_base + clk->div.offset); in iproc_asiu_clk_set_rate()
172 writel(val, asiu->div_base + clk->div.offset); in iproc_asiu_clk_set_rate()
210 asiu->div_base = of_iomap(node, 0); in iproc_asiu_setup()
211 if (WARN_ON(!asiu->div_base)) in iproc_asiu_setup()
261 iounmap(asiu->div_base); in iproc_asiu_setup()
/kernel/linux/linux-5.10/drivers/pwm/
Dpwm-samsung.c128 bits = (fls(divisor) - 1) - pwm->variant.div_base; in pwm_samsung_set_divisor()
198 for (div = variant->div_base; div < 4; ++div) in pwm_samsung_calc_tin()
206 div = variant->div_base; in pwm_samsung_calc_tin()
440 .div_base = 1,
447 .div_base = 0,
454 .div_base = 0,
461 .div_base = 0,
/kernel/linux/linux-5.10/drivers/clocksource/
Dsamsung_pwm_timer.c108 bits = (fls(divisor) - 1) - pwm.variant.div_base; in samsung_timer_set_divisor()
452 .div_base = 1,
465 .div_base = 0,
478 .div_base = 0,
491 .div_base = 0,
/kernel/linux/linux-5.10/include/clocksource/
Dsamsung_pwm.h23 u8 div_base; member
/kernel/linux/linux-5.10/arch/arm/mach-s3c/
Ds3c64xx.c171 .div_base = 0,
Ds3c24xx.c201 .div_base = 1,