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Searched refs:dpll (Results 1 – 25 of 68) sorted by relevance

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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ti/
Ddpll.txt18 "ti,omap3-dpll-clock",
19 "ti,omap3-dpll-core-clock",
20 "ti,omap3-dpll-per-clock",
21 "ti,omap3-dpll-per-j-type-clock",
22 "ti,omap4-dpll-clock",
23 "ti,omap4-dpll-x2-clock",
24 "ti,omap4-dpll-core-clock",
25 "ti,omap4-dpll-m4xen-clock",
26 "ti,omap4-dpll-j-type-clock",
27 "ti,omap5-mpu-dpll-clock",
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/gma500/
Dpsb_intel_display.c105 u32 dpll = 0, fp = 0, dspcntr, pipeconf; in psb_intel_crtc_mode_set() local
152 dpll = DPLL_VGA_MODE_DIS; in psb_intel_crtc_mode_set()
154 dpll |= DPLLB_MODE_LVDS; in psb_intel_crtc_mode_set()
155 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
157 dpll |= DPLLB_MODE_DAC_SERIAL; in psb_intel_crtc_mode_set()
161 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
162 dpll |= in psb_intel_crtc_mode_set()
167 dpll |= (1 << (clock.p1 - 1)) << 16; in psb_intel_crtc_mode_set()
170 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in psb_intel_crtc_mode_set()
173 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in psb_intel_crtc_mode_set()
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Doaktrail_crtc.c242 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
244 REG_WRITE_WITH_AUX(map->dpll, temp, i); in oaktrail_crtc_dpms()
245 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
248 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
250 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
253 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
255 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
314 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
316 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
318 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
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Dmdfld_intel_display.c243 temp = REG_READ(map->dpll); in mdfld_disable_crtc()
249 REG_WRITE(map->dpll, temp); in mdfld_disable_crtc()
250 REG_READ(map->dpll); in mdfld_disable_crtc()
257 REG_WRITE(map->dpll, temp | MDFLD_PWR_GATE_EN); in mdfld_disable_crtc()
299 temp = REG_READ(map->dpll); in mdfld_crtc_dpms()
306 REG_WRITE(map->dpll, temp); in mdfld_crtc_dpms()
311 REG_WRITE(map->dpll, temp); in mdfld_crtc_dpms()
312 REG_READ(map->dpll); in mdfld_crtc_dpms()
316 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in mdfld_crtc_dpms()
317 REG_READ(map->dpll); in mdfld_crtc_dpms()
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Dmdfld_device.c188 pipe->dpll = PSB_RVDC32(map->dpll); in mdfld_save_display_registers()
242 u32 dpll; in mdfld_restore_display_registers() local
249 u32 dpll_val = pipe->dpll; in mdfld_restore_display_registers()
274 PSB_WVDC32(dpll_val & ~DPLL_VCO_ENABLE, map->dpll); in mdfld_restore_display_registers()
275 PSB_RVDC32(map->dpll); in mdfld_restore_display_registers()
280 dpll = PSB_RVDC32(map->dpll); in mdfld_restore_display_registers()
282 if (!(dpll & DPLL_VCO_ENABLE)) { in mdfld_restore_display_registers()
286 if (dpll & MDFLD_PWR_GATE_EN) { in mdfld_restore_display_registers()
287 dpll &= ~MDFLD_PWR_GATE_EN; in mdfld_restore_display_registers()
288 PSB_WVDC32(dpll, map->dpll); in mdfld_restore_display_registers()
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Dcdv_intel_display.c583 u32 dpll = 0, dspcntr, pipeconf; in cdv_intel_crtc_mode_set() local
662 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()
666 dpll |= 3; in cdv_intel_crtc_mode_set()
679 dpll |= DPLL_SYNCLOCK_ENABLE; in cdv_intel_crtc_mode_set()
725 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); in cdv_intel_crtc_mode_set()
726 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
761 dpll |= DPLL_VCO_ENABLE; in cdv_intel_crtc_mode_set()
770 REG_WRITE(map->dpll, in cdv_intel_crtc_mode_set()
771 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); in cdv_intel_crtc_mode_set()
772 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
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Dgma_display.c215 temp = REG_READ(map->dpll); in gma_crtc_dpms()
217 REG_WRITE(map->dpll, temp); in gma_crtc_dpms()
218 REG_READ(map->dpll); in gma_crtc_dpms()
221 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
222 REG_READ(map->dpll); in gma_crtc_dpms()
225 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
226 REG_READ(map->dpll); in gma_crtc_dpms()
303 temp = REG_READ(map->dpll); in gma_crtc_dpms()
305 REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); in gma_crtc_dpms()
306 REG_READ(map->dpll); in gma_crtc_dpms()
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Doaktrail_hdmi.c282 u32 dspcntr, pipeconf, dpll, temp; in oaktrail_crtc_hdmi_mode_set() local
292 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
293 if ((dpll & DPLL_PWRDN) == 0) { in oaktrail_crtc_hdmi_mode_set()
294 REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET)); in oaktrail_crtc_hdmi_mode_set()
308 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
309 dpll &= ~DPLL_PDIV_MASK; in oaktrail_crtc_hdmi_mode_set()
310 dpll &= ~(DPLL_PWRDN | DPLL_RESET); in oaktrail_crtc_hdmi_mode_set()
314 REG_WRITE(DPLL_CTRL, (dpll | (clock.np << DPLL_PDIV_SHIFT) | DPLL_ENSTAT | DPLL_DITHEN)); in oaktrail_crtc_hdmi_mode_set()
Doaktrail_device.c202 p->dpll = PSB_RVDC32(MRST_DPLL_A); in oaktrail_save_display_registers()
319 PSB_WVDC32(p->dpll, MRST_DPLL_A); in oaktrail_restore_display_registers()
460 .dpll = MRST_DPLL_A,
484 .dpll = DPLL_B,
/kernel/linux/linux-5.10/arch/arm/mach-omap1/
Dsram.S36 strh r0, [r2] @ set dpll into bypass mode
41 strh r0, [r2] @ write new dpll value
49 lock: ldrh r4, [r2], #0 @ read back dpll value
52 tst r4, #1 << 0 @ dpll rate locked?
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
Dintel_dpll_mgr.c71 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) { in intel_atomic_duplicate_dpll_state()
72 struct intel_shared_dpll *pll = &dev_priv->dpll.shared_dplls[i]; in intel_atomic_duplicate_dpll_state()
107 return &dev_priv->dpll.shared_dplls[id]; in intel_get_shared_dpll_by_id()
122 long pll_idx = pll - dev_priv->dpll.shared_dplls; in intel_get_shared_dpll_id()
126 pll_idx >= dev_priv->dpll.num_shared_dpll)) in intel_get_shared_dpll_id()
178 mutex_lock(&dev_priv->dpll.lock); in intel_prepare_shared_dpll()
187 mutex_unlock(&dev_priv->dpll.lock); in intel_prepare_shared_dpll()
207 mutex_lock(&dev_priv->dpll.lock); in intel_enable_shared_dpll()
233 mutex_unlock(&dev_priv->dpll.lock); in intel_enable_shared_dpll()
256 mutex_lock(&dev_priv->dpll.lock); in intel_disable_shared_dpll()
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Dintel_display.c578 static int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params()
590 static u32 i9xx_dpll_compute_m(struct dpll *dpll) in i9xx_dpll_compute_m() argument
592 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
595 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) in i9xx_calc_dpll_params()
607 static int vlv_calc_dpll_params(int refclk, struct dpll *clock) in vlv_calc_dpll_params()
619 int chv_calc_dpll_params(int refclk, struct dpll *clock) in chv_calc_dpll_params()
638 const struct dpll *clock) in intel_pll_is_valid()
711 int target, int refclk, struct dpll *match_clock, in i9xx_find_best_dpll()
712 struct dpll *best_clock) in i9xx_find_best_dpll()
715 struct dpll clock; in i9xx_find_best_dpll()
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Dintel_dvo.c457 u32 dpll[I915_MAX_PIPES]; in intel_dvo_init() local
494 dpll[pipe] = intel_de_read(dev_priv, DPLL(pipe)); in intel_dvo_init()
496 dpll[pipe] | DPLL_DVO_2X_MODE); in intel_dvo_init()
503 intel_de_write(dev_priv, DPLL(pipe), dpll[pipe]); in intel_dvo_init()
Dintel_display.h31 struct dpll;
571 const struct dpll *dpll);
584 struct dpll *best_clock);
585 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
/kernel/linux/linux-5.10/drivers/ata/
Dpata_hpt3x2n.c317 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_defer() local
324 if ((flags & USE_DPLL) != dpll && alt->qc_active) in hpt3x2n_qc_defer()
333 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_issue() local
335 if ((flags & USE_DPLL) != dpll) { in hpt3x2n_qc_issue()
337 flags |= dpll; in hpt3x2n_qc_issue()
340 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); in hpt3x2n_qc_issue()
Dpata_hpt37x.c980 int dpll, adjust; in hpt37x_init_one() local
983 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2; in hpt37x_init_one()
985 f_low = (MHz[clock_slot] * 48) / MHz[dpll]; in hpt37x_init_one()
1013 if (dpll == 3) in hpt37x_init_one()
1019 MHz[clock_slot], MHz[dpll]); in hpt37x_init_one()
/kernel/linux/linux-5.10/drivers/gpu/drm/rcar-du/
Drcar_du_crtc.c85 struct dpll_info *dpll, in rcar_du_dpll_divider() argument
149 dpll->n = n; in rcar_du_dpll_divider()
150 dpll->m = m; in rcar_du_dpll_divider()
151 dpll->fdpll = fdpll; in rcar_du_dpll_divider()
152 dpll->output = output; in rcar_du_dpll_divider()
164 dpll->output, dpll->fdpll, dpll->n, dpll->m, best_diff); in rcar_du_dpll_divider()
224 struct dpll_info dpll = { 0 }; in rcar_du_crtc_set_display_timing() local
248 rcar_du_dpll_divider(rcrtc, &dpll, extclk, target); in rcar_du_crtc_set_display_timing()
251 | DPLLCR_FDPLL(dpll.fdpll) in rcar_du_crtc_set_display_timing()
252 | DPLLCR_N(dpll.n) | DPLLCR_M(dpll.m) in rcar_du_crtc_set_display_timing()
/kernel/linux/linux-5.10/drivers/video/fbdev/intelfb/
Dintelfbhw.c684 static void intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll, in intelfbhw_get_p1p2() argument
690 if (dpll & DPLL_P1_FORCE_DIV2) in intelfbhw_get_p1p2()
693 p1 = (dpll >> DPLL_P1_SHIFT) & 0xff; in intelfbhw_get_p1p2()
697 p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK; in intelfbhw_get_p1p2()
699 if (dpll & DPLL_P1_FORCE_DIV2) in intelfbhw_get_p1p2()
702 p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK; in intelfbhw_get_p1p2()
703 p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK; in intelfbhw_get_p1p2()
1045 u32 *dpll, *fp0, *fp1; in intelfbhw_mode_to_hw() local
1060 dpll = &hw->dpll_b; in intelfbhw_mode_to_hw()
1072 dpll = &hw->dpll_a; in intelfbhw_mode_to_hw()
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Domap54xx-clocks.dtsi104 compatible = "ti,omap4-dpll-m4xen-clock";
111 compatible = "ti,omap4-dpll-x2-clock";
177 compatible = "ti,omap4-dpll-core-clock";
184 compatible = "ti,omap4-dpll-x2-clock";
312 compatible = "ti,omap4-dpll-clock";
321 compatible = "ti,omap4-dpll-x2-clock";
357 compatible = "ti,omap5-mpu-dpll-clock";
521 compatible = "ti,omap4-dpll-clock";
528 compatible = "ti,omap4-dpll-x2-clock";
588 compatible = "ti,omap4-dpll-clock";
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Ddra7xx-clocks.dtsi198 compatible = "ti,omap4-dpll-m4xen-clock";
205 compatible = "ti,omap4-dpll-x2-clock";
261 compatible = "ti,omap4-dpll-core-clock";
268 compatible = "ti,omap4-dpll-x2-clock";
293 compatible = "ti,omap5-mpu-dpll-clock";
335 compatible = "ti,omap4-dpll-clock";
373 compatible = "ti,omap4-dpll-clock";
411 compatible = "ti,omap4-dpll-clock";
460 compatible = "ti,omap4-dpll-clock";
486 compatible = "ti,omap4-dpll-clock";
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Dam43xx-clocks.dtsi205 compatible = "ti,am3-dpll-core-clock";
212 compatible = "ti,am3-dpll-x2-clock";
251 compatible = "ti,am3-dpll-clock";
277 compatible = "ti,am3-dpll-clock";
295 compatible = "ti,am3-dpll-clock";
314 compatible = "ti,am3-dpll-j-type-clock";
558 compatible = "ti,am3-dpll-clock";
627 compatible = "ti,am3-dpll-x2-clock";
Dam33xx-clocks.dtsi165 compatible = "ti,am3-dpll-core-clock";
172 compatible = "ti,am3-dpll-x2-clock";
205 compatible = "ti,am3-dpll-clock";
221 compatible = "ti,am3-dpll-no-gate-clock";
245 compatible = "ti,am3-dpll-no-gate-clock";
262 compatible = "ti,am3-dpll-no-gate-j-type-clock";
Domap44xx-clocks.dtsi134 compatible = "ti,omap4-dpll-m4xen-clock";
141 compatible = "ti,omap4-dpll-x2-clock";
196 compatible = "ti,omap4-dpll-core-clock";
203 compatible = "ti,omap4-dpll-x2-clock";
346 compatible = "ti,omap4-dpll-clock";
355 compatible = "ti,omap4-dpll-x2-clock";
387 compatible = "ti,omap4-dpll-clock";
566 compatible = "ti,omap4-dpll-clock";
582 compatible = "ti,omap4-dpll-x2-clock";
667 compatible = "ti,omap4-dpll-j-type-clock";
/kernel/linux/linux-5.10/arch/arm64/boot/dts/sprd/
Dsharkl3.dtsi123 dpll: dpll { label
124 compatible = "sprd,sc9863a-dpll";
/kernel/linux/linux-5.10/drivers/ptp/
Dptp_clockmatrix.c1577 u16 dpll; in _enable_pll_tod_sync() local
1585 dpll = DPLL_0; in _enable_pll_tod_sync()
1592 dpll = DPLL_1; in _enable_pll_tod_sync()
1599 dpll = DPLL_2; in _enable_pll_tod_sync()
1606 dpll = DPLL_3; in _enable_pll_tod_sync()
1613 dpll = DPLL_4; in _enable_pll_tod_sync()
1618 dpll = DPLL_5; in _enable_pll_tod_sync()
1625 dpll = DPLL_6; in _enable_pll_tod_sync()
1632 dpll = DPLL_7; in _enable_pll_tod_sync()
1672 err = idtcm_read(idtcm, dpll, DPLL_TOD_SYNC_CFG, &val, sizeof(val)); in _enable_pll_tod_sync()
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