| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | vega12_hwmgr.c | 619 dpm_table->dpm_levels[i].value = clk; in vega12_setup_single_dpm_table()
620 dpm_table->dpm_levels[i].enabled = true; in vega12_setup_single_dpm_table()
653 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100; in vega12_setup_default_dpm_tables()
666 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100; in vega12_setup_default_dpm_tables()
679 dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100; in vega12_setup_default_dpm_tables()
692 dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100; in vega12_setup_default_dpm_tables()
705 dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100; in vega12_setup_default_dpm_tables()
718 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100; in vega12_setup_default_dpm_tables()
731 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100; in vega12_setup_default_dpm_tables()
796 dpm_table->dpm_levels[min_level].value;
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| D | vega20_hwmgr.c | 576 dpm_table->dpm_levels[i].value = clk; in vega20_setup_single_dpm_table()
577 dpm_table->dpm_levels[i].enabled = true; in vega20_setup_single_dpm_table()
598 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100; in vega20_setup_gfxclk_dpm_table()
619 dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100; in vega20_setup_memclk_dpm_table()
651 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100; in vega20_setup_default_dpm_tables()
678 dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100; in vega20_setup_default_dpm_tables()
691 dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100; in vega20_setup_default_dpm_tables()
704 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100; in vega20_setup_default_dpm_tables()
717 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100; in vega20_setup_default_dpm_tables()
763 dpm_table->dpm_levels[0].value = data->vbios_boot_state.fclock / 100; in vega20_setup_default_dpm_tables()
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| D | vega10_hwmgr.c | 1240 if (i == 0 || dpm_table->dpm_levels[dpm_table->count - 1].value <= in vega10_setup_default_single_dpm_table()
1242 dpm_table->dpm_levels[dpm_table->count].value = in vega10_setup_default_single_dpm_table()
1244 dpm_table->dpm_levels[dpm_table->count].enabled = true; in vega10_setup_default_single_dpm_table()
1358 dpm_table->dpm_levels[dpm_table->count-1].value; in vega10_setup_default_dpm_tables()
1369 dpm_table->dpm_levels[dpm_table->count-1].value; in vega10_setup_default_dpm_tables()
1375 if (i == 0 || dpm_table->dpm_levels in vega10_setup_default_dpm_tables()
1378 dpm_table->dpm_levels[dpm_table->count].value = in vega10_setup_default_dpm_tables()
1380 dpm_table->dpm_levels[dpm_table->count].enabled = in vega10_setup_default_dpm_tables()
1391 if (i == 0 || dpm_table->dpm_levels in vega10_setup_default_dpm_tables()
1394 dpm_table->dpm_levels[dpm_table->count].value = in vega10_setup_default_dpm_tables()
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| D | smu7_hwmgr.c | 745 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value != in smu7_setup_dpm_tables_v0()
747 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = in smu7_setup_dpm_tables_v0()
749 …data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = (i == 0) ? 1 : 0; in smu7_setup_dpm_tables_v0()
759 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value != in smu7_setup_dpm_tables_v0()
761 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = in smu7_setup_dpm_tables_v0()
763 …data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = (i == 0) ? 1 : 0; in smu7_setup_dpm_tables_v0()
770 data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v; in smu7_setup_dpm_tables_v0()
771 data->dpm_table.vddc_table.dpm_levels[i].param1 = std_voltage_table->entries[i].Leakage; in smu7_setup_dpm_tables_v0()
773 data->dpm_table.vddc_table.dpm_levels[i].enabled = true; in smu7_setup_dpm_tables_v0()
782 data->dpm_table.vddci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v; in smu7_setup_dpm_tables_v0()
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| D | smu7_hwmgr.h | 100 struct smu7_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; member
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| D | vega10_hwmgr.h | 136 struct vega10_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; member
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| D | vega12_hwmgr.h | 110 struct vega12_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; member
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| D | vega20_hwmgr.h | 162 struct vega20_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; member
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| D | navi10_ppt.c | 651 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in navi10_set_default_dpm_table()
652 dpm_table->dpm_levels[0].enabled = true; in navi10_set_default_dpm_table()
653 dpm_table->min = dpm_table->dpm_levels[0].value; in navi10_set_default_dpm_table()
654 dpm_table->max = dpm_table->dpm_levels[0].value; in navi10_set_default_dpm_table()
669 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; in navi10_set_default_dpm_table()
670 dpm_table->dpm_levels[0].enabled = true; in navi10_set_default_dpm_table()
671 dpm_table->min = dpm_table->dpm_levels[0].value; in navi10_set_default_dpm_table()
672 dpm_table->max = dpm_table->dpm_levels[0].value; in navi10_set_default_dpm_table()
687 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in navi10_set_default_dpm_table()
688 dpm_table->dpm_levels[0].enabled = true; in navi10_set_default_dpm_table()
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| D | sienna_cichlid_ppt.c | 568 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in sienna_cichlid_set_default_dpm_table()
569 dpm_table->dpm_levels[0].enabled = true; in sienna_cichlid_set_default_dpm_table()
570 dpm_table->min = dpm_table->dpm_levels[0].value; in sienna_cichlid_set_default_dpm_table()
571 dpm_table->max = dpm_table->dpm_levels[0].value; in sienna_cichlid_set_default_dpm_table()
586 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; in sienna_cichlid_set_default_dpm_table()
587 dpm_table->dpm_levels[0].enabled = true; in sienna_cichlid_set_default_dpm_table()
588 dpm_table->min = dpm_table->dpm_levels[0].value; in sienna_cichlid_set_default_dpm_table()
589 dpm_table->max = dpm_table->dpm_levels[0].value; in sienna_cichlid_set_default_dpm_table()
604 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in sienna_cichlid_set_default_dpm_table()
605 dpm_table->dpm_levels[0].enabled = true; in sienna_cichlid_set_default_dpm_table()
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| D | arcturus_ppt.c | 319 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; in arcturus_set_default_dpm_table()
320 dpm_table->dpm_levels[0].enabled = true; in arcturus_set_default_dpm_table()
321 dpm_table->min = dpm_table->dpm_levels[0].value; in arcturus_set_default_dpm_table()
322 dpm_table->max = dpm_table->dpm_levels[0].value; in arcturus_set_default_dpm_table()
337 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; in arcturus_set_default_dpm_table()
338 dpm_table->dpm_levels[0].enabled = true; in arcturus_set_default_dpm_table()
339 dpm_table->min = dpm_table->dpm_levels[0].value; in arcturus_set_default_dpm_table()
340 dpm_table->max = dpm_table->dpm_levels[0].value; in arcturus_set_default_dpm_table()
355 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in arcturus_set_default_dpm_table()
356 dpm_table->dpm_levels[0].enabled = true; in arcturus_set_default_dpm_table()
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| D | arcturus_ppt.h | 49 struct arcturus_dpm_level dpm_levels[MAX_DPM_NUMBER]; member
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| D | smu_v11_0.c | 1911 single_dpm_table->dpm_levels[i].value = clk; in smu_v11_0_set_single_dpm_table()
1912 single_dpm_table->dpm_levels[i].enabled = true; in smu_v11_0_set_single_dpm_table()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
| D | ci_dpm.c | 2543 pi->dpm_table.sclk_table.dpm_levels[i].value, in ci_do_program_memory_timing_parameters()
2544 pi->dpm_table.mclk_table.dpm_levels[j].value, in ci_do_program_memory_timing_parameters()
2602 if (dpm_table->dpm_levels[i-1].enabled) in ci_get_dpm_level_enable_mask_value()
2620 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value; in ci_populate_smc_link_level()
2622 r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in ci_populate_smc_link_level()
3276 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
3322 if (dpm_table->mclk_table.dpm_levels[i].value == 0) in ci_populate_all_memory_levels()
3325 dpm_table->mclk_table.dpm_levels[i].value, in ci_populate_all_memory_levels()
3367 dpm_table->dpm_levels[i].enabled = false; in ci_reset_single_dpm_table()
3373 dpm_table->dpm_levels[index].value = pcie_gen; in ci_setup_pcie_table_entry()
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| D | ci_dpm.h | 65 struct ci_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; member
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| D | fiji_smumgr.c | 839 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in fiji_populate_smc_link_level()
841 dpm_table->pcie_speed_table.dpm_levels[i].param1); in fiji_populate_smc_link_level()
1025 dpm_table->sclk_table.dpm_levels[i].value, in fiji_populate_all_graphic_levels()
1236 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in fiji_populate_all_memory_levels()
1240 dpm_table->mclk_table.dpm_levels[i].value, in fiji_populate_all_memory_levels()
1317 data->dpm_table.sclk_table.dpm_levels[0].value; in fiji_populate_smc_acpi_level()
1375 data->dpm_table.mclk_table.dpm_levels[0].value; in fiji_populate_smc_acpi_level()
1396 data->dpm_table.mclk_table.dpm_levels[0].value, in fiji_populate_smc_acpi_level()
1536 data->dpm_table.sclk_table.dpm_levels[i].value, in fiji_program_memory_timing_parameters()
1537 data->dpm_table.mclk_table.dpm_levels[j].value, in fiji_program_memory_timing_parameters()
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| D | polaris10_smumgr.c | 779 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in polaris10_populate_smc_link_level()
781 dpm_table->pcie_speed_table.dpm_levels[i].param1); in polaris10_populate_smc_link_level()
1005 dpm_table->sclk_table.dpm_levels[i].value, in polaris10_populate_all_graphic_levels()
1141 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in polaris10_populate_all_memory_levels()
1145 dpm_table->mclk_table.dpm_levels[i].value, in polaris10_populate_all_memory_levels()
1263 data->dpm_table.mclk_table.dpm_levels[0].value, in polaris10_populate_smc_acpi_level()
1374 hw_data->dpm_table.sclk_table.dpm_levels[i].value, in polaris10_program_memory_timing_parameters()
1375 hw_data->dpm_table.mclk_table.dpm_levels[j].value, in polaris10_program_memory_timing_parameters()
1378 result = atomctrl_set_ac_timing_ai(hwmgr, hw_data->dpm_table.mclk_table.dpm_levels[j].value, j); in polaris10_program_memory_timing_parameters()
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| D | iceland_smumgr.c | 774 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in iceland_populate_smc_link_level()
776 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in iceland_populate_smc_link_level()
982 dpm_table->sclk_table.dpm_levels[i].value, in iceland_populate_all_graphic_levels()
1362 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in iceland_populate_all_memory_levels()
1364 result = iceland_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, in iceland_populate_all_memory_levels()
1624 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in iceland_program_memory_timing_parameters()
1625 data->dpm_table.mclk_table.dpm_levels[j].value, in iceland_program_memory_timing_parameters()
1764 data->dpm_table.mclk_table.dpm_levels[i].value, in iceland_convert_mc_reg_table_to_smc()
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| D | vegam_smumgr.c | 582 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in vegam_populate_smc_link_level()
584 dpm_table->pcie_speed_table.dpm_levels[i].param1); in vegam_populate_smc_link_level()
892 dpm_table->sclk_table.dpm_levels[i].value, in vegam_populate_all_graphic_levels()
1051 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in vegam_populate_all_memory_levels()
1055 dpm_table->mclk_table.dpm_levels[i].value, in vegam_populate_all_memory_levels()
1291 hw_data->dpm_table.sclk_table.dpm_levels[i].value, in vegam_program_memory_timing_parameters()
1292 hw_data->dpm_table.mclk_table.dpm_levels[j].value, in vegam_program_memory_timing_parameters()
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| D | ci_smumgr.c | 487 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
1006 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in ci_populate_smc_link_level()
1008 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in ci_populate_smc_link_level()
1316 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in ci_populate_all_memory_levels()
1318 result = ci_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, in ci_populate_all_memory_levels()
1662 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in ci_program_memory_timing_parameters()
1663 data->dpm_table.mclk_table.dpm_levels[j].value, in ci_program_memory_timing_parameters()
1798 data->dpm_table.mclk_table.dpm_levels[i].value, in ci_convert_mc_reg_table_to_smc()
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| D | tonga_smumgr.c | 517 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in tonga_populate_smc_link_level()
519 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in tonga_populate_smc_link_level()
712 dpm_table->sclk_table.dpm_levels[i].value, in tonga_populate_all_graphic_levels()
1108 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in tonga_populate_all_memory_levels()
1113 dpm_table->mclk_table.dpm_levels[i].value, in tonga_populate_all_memory_levels()
1500 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in tonga_program_memory_timing_parameters()
1501 data->dpm_table.mclk_table.dpm_levels[j].value, in tonga_program_memory_timing_parameters()
2143 data->dpm_table.mclk_table.dpm_levels[i].value, in tonga_convert_mc_reg_table_to_smc()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/inc/ |
| D | smu_v11_0.h | 84 struct smu_11_0_dpm_clk_level dpm_levels[MAX_DPM_LEVELS]; member
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