Searched refs:dram_clock_change_latency_us (Results 1 – 14 of 14) sorted by relevance
71 uint32_t dram_clock_change_latency_us; member
211 .dram_clock_change_latency_us = 404,1788 dcn3_0_soc.dram_clock_change_latency_us = in init_soc_bounding_box()1789 fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us); in init_soc_bounding_box()1837 dcn3_0_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10; in init_soc_bounding_box()2232 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_calculate_wm_and_dlg()2278 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->dummy_pstate_table[… in dcn30_calculate_wm_and_dlg()2286 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->dummy_pstate_table[… in dcn30_calculate_wm_and_dlg()2315 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_calculate_wm_and_dlg()2357 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn30_calculate_wm_and_dlg()
110 double dram_clock_change_latency_us; member
229 mode_lib->vba.DRAMClockChangeLatency = soc->dram_clock_change_latency_us; in fetch_socbb_params()230 mode_lib->vba.DummyPStateCheck = soc->dram_clock_change_latency_us == soc->dummy_pstate_latency_us; in fetch_socbb_params()
1308 mode_lib->soc.dram_clock_change_latency_us in dml1_rq_dlg_get_dlg_params()1324 (double) mode_lib->soc.dram_clock_change_latency_us); in dml1_rq_dlg_get_dlg_params()
330 .dram_clock_change_latency_us = 404.0,441 .dram_clock_change_latency_us = 404.0,3210 p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;3234 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latenc…3248 context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us;3567 if ((int)(bb->dram_clock_change_latency_us * 1000)3570 bb->dram_clock_change_latency_us =3693 dcn2_0_nv12_soc.dram_clock_change_latency_us =3694 fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us);3696 dcn2_0_nv12_soc.dram_clock_change_latency_us = 10;
298 .dram_clock_change_latency_us = 23.84,1033 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; in calculate_wm_set_for_vlevel()1041 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; in calculate_wm_set_for_vlevel()1053 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached; in calculate_wm_set_for_vlevel()
110 double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us; in dcn3_build_wm_range_table()
1094 line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us in dml20v2_rq_dlg_get_dlg_params()
1093 line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us in dml20_rq_dlg_get_dlg_params()
130 .dram_clock_change_latency_us = 17.0,
1141 mode_lib->soc.dram_clock_change_latency_us in dml_rq_dlg_get_dlg_params()
1333 line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us in dml_rq_dlg_get_dlg_params()
1763 dc->dml.soc.dram_clock_change_latency_us = dc->dcn_soc->dram_clock_change_latency; in dcn_bw_sync_calcs_and_dml()