| /kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
| D | rv770_dpm.h | 181 u32 engine_clock,
184 u32 engine_clock, u32 memory_clock,
202 int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock,
205 u32 engine_clock, u32 memory_clock,
227 u32 engine_clock);
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| D | rv740_dpm.c | 120 int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, in rv740_populate_sclk_value() argument
137 engine_clock, false, ÷rs); in rv740_populate_sclk_value()
143 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in rv740_populate_sclk_value()
160 u32 vco_freq = engine_clock * dividers.post_div; in rv740_populate_sclk_value()
176 sclk->sclk_value = cpu_to_be32(engine_clock); in rv740_populate_sclk_value()
187 u32 engine_clock, u32 memory_clock, in rv740_populate_mclk_value() argument
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| D | rv730_dpm.c | 40 u32 engine_clock, in rv730_populate_sclk_value() argument
57 engine_clock, false, ÷rs); in rv730_populate_sclk_value()
69 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv730_populate_sclk_value()
92 u32 vco_freq = engine_clock * post_divider; in rv730_populate_sclk_value()
108 sclk->sclk_value = cpu_to_be32(engine_clock); in rv730_populate_sclk_value()
119 u32 engine_clock, u32 memory_clock, in rv730_populate_mclk_value() argument
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| D | cypress_dpm.h | 125 u32 engine_clock, u32 memory_clock);
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| D | rv770_dpm.c | 386 u32 engine_clock, u32 memory_clock, in rv770_populate_mclk_value() argument
484 u32 engine_clock, in rv770_populate_sclk_value() argument
506 engine_clock, false, ÷rs); in rv770_populate_sclk_value()
517 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv770_populate_sclk_value()
539 u32 vco_freq = engine_clock * post_divider; in rv770_populate_sclk_value()
555 sclk->sclk_value = cpu_to_be32(engine_clock); in rv770_populate_sclk_value()
722 u32 engine_clock) in rv770_calculate_memory_refresh_rate() argument
733 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; in rv770_calculate_memory_refresh_rate()
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| D | ci_dpm.c | 2481 const u32 engine_clock, in ci_register_patching_mc_arb() argument
2495 tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff; in ci_register_patching_mc_arb()
2499 tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff; in ci_register_patching_mc_arb()
3145 u32 engine_clock, in ci_calculate_sclk_params() argument
3161 engine_clock, false, ÷rs); in ci_calculate_sclk_params()
3174 u32 vco_freq = engine_clock * dividers.post_div; in ci_calculate_sclk_params()
3190 sclk->SclkFrequency = engine_clock; in ci_calculate_sclk_params()
3201 u32 engine_clock, in ci_populate_single_graphic_level() argument
3208 ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level); in ci_populate_single_graphic_level()
3214 engine_clock, &graphic_level->MinVddc); in ci_populate_single_graphic_level()
[all …]
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| D | ni_dpm.c | 1998 u32 engine_clock, in ni_calculate_sclk_params() argument
2017 engine_clock, false, ÷rs); in ni_calculate_sclk_params()
2024 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834; in ni_calculate_sclk_params()
2041 u32 vco_freq = engine_clock * dividers.post_div; in ni_calculate_sclk_params()
2057 sclk->sclk_value = engine_clock; in ni_calculate_sclk_params()
2069 u32 engine_clock, in ni_populate_sclk_value() argument
2075 ret = ni_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); in ni_populate_sclk_value()
2160 u32 engine_clock, in ni_populate_mclk_value() argument
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| D | si_dpm.c | 1740 u32 engine_clock,
4257 u32 engine_clock) in si_calculate_memory_refresh_rate() argument
4270 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; in si_calculate_memory_refresh_rate()
4765 u32 engine_clock, in si_calculate_sclk_params() argument
4784 engine_clock, false, ÷rs); in si_calculate_sclk_params()
4790 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in si_calculate_sclk_params()
4807 u32 vco_freq = engine_clock * dividers.post_div; in si_calculate_sclk_params()
4823 sclk->sclk_value = engine_clock; in si_calculate_sclk_params()
4835 u32 engine_clock, in si_populate_sclk_value() argument
4841 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); in si_populate_sclk_value()
[all …]
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| D | cypress_dpm.c | 475 u32 engine_clock, u32 memory_clock, in cypress_populate_mclk_value() argument
905 u32 engine_clock, u32 memory_clock) in cypress_calculate_burst_time() argument
909 u32 result = (4 * multiplier * engine_clock) / (memory_clock / 2); in cypress_calculate_burst_time()
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| D | rv6xx_dpm.c | 782 u32 engine_clock) in calculate_memory_refresh_rate() argument
791 return ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; in calculate_memory_refresh_rate()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | smu7_hwmgr.c | 3017 if (smu7_ps->performance_levels[i].engine_clock > max_limits->sclk) in smu7_apply_state_adjust_rules()
3018 smu7_ps->performance_levels[i].engine_clock = max_limits->sclk; in smu7_apply_state_adjust_rules()
3062 sclk = smu7_ps->performance_levels[0].engine_clock; in smu7_apply_state_adjust_rules()
3077 smu7_ps->performance_levels[0].engine_clock = sclk; in smu7_apply_state_adjust_rules()
3080 smu7_ps->performance_levels[1].engine_clock = in smu7_apply_state_adjust_rules()
3081 (smu7_ps->performance_levels[1].engine_clock >= in smu7_apply_state_adjust_rules()
3082 smu7_ps->performance_levels[0].engine_clock) ? in smu7_apply_state_adjust_rules()
3083 smu7_ps->performance_levels[1].engine_clock : in smu7_apply_state_adjust_rules()
3084 smu7_ps->performance_levels[0].engine_clock; in smu7_apply_state_adjust_rules()
3102 smu7_ps->performance_levels[i].engine_clock = stable_pstate_sclk; in smu7_apply_state_adjust_rules()
[all …]
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| D | ppatomctrl.h | 286 …t_engine_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t engine_clock, pp_atomctrl_in…
288 extern int atomctrl_set_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, ui…
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| D | smu10_hwmgr.h | 76 uint32_t engine_clock; member
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| D | smu7_hwmgr.h | 56 uint32_t engine_clock; member
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| D | smu10_hwmgr.c | 813 smu10_ps->levels[index].engine_clock = 0; in smu10_dpm_get_pp_table_entry_callback()
1041 clock_info->min_eng_clk = ps->levels[0].engine_clock / (1 << (ps->levels[0].ss_divider_index)); in smu10_get_current_shallow_sleep_clocks()
1042 …clock_info->max_eng_clk = ps->levels[ps->level - 1].engine_clock / (1 << (ps->levels[ps->level - 1… in smu10_get_current_shallow_sleep_clocks()
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| D | ppatomctrl.c | 174 uint32_t engine_clock, in atomctrl_set_engine_dram_timings_rv770() argument
183 cpu_to_le32((engine_clock & SET_CLOCK_FREQ_MASK) | in atomctrl_set_engine_dram_timings_rv770()
1290 const uint32_t engine_clock, in atomctrl_get_engine_clock_spread_spectrum() argument
1294 ASIC_INTERNAL_ENGINE_SS, engine_clock, ssInfo); in atomctrl_get_engine_clock_spread_spectrum()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| D | iceland_smumgr.c | 796 uint32_t engine_clock, SMU71_Discrete_GraphicsLevel *sclk) in iceland_calculate_sclk_params() argument
811 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, ÷rs); in iceland_calculate_sclk_params()
842 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div; in iceland_calculate_sclk_params()
863 sclk->SclkFrequency = engine_clock; in iceland_calculate_sclk_params()
892 uint32_t engine_clock, in iceland_populate_single_graphic_level() argument
898 result = iceland_calculate_sclk_params(hwmgr, engine_clock, graphic_level); in iceland_populate_single_graphic_level()
902 hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock, in iceland_populate_single_graphic_level()
908 graphic_level->SclkFrequency = engine_clock; in iceland_populate_single_graphic_level()
914 engine_clock, in iceland_populate_single_graphic_level()
937 smu7_get_sleep_divider_id_from_clock(engine_clock, in iceland_populate_single_graphic_level()
[all …]
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| D | tonga_smumgr.c | 539 uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk) in tonga_calculate_sclk_params() argument
554 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, ÷rs); in tonga_calculate_sclk_params()
585 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div; in tonga_calculate_sclk_params()
606 sclk->SclkFrequency = engine_clock; in tonga_calculate_sclk_params()
617 uint32_t engine_clock, in tonga_populate_single_graphic_level() argument
627 result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level); in tonga_populate_single_graphic_level()
636 vdd_dep_table, engine_clock, in tonga_populate_single_graphic_level()
643 graphic_level->SclkFrequency = engine_clock; in tonga_populate_single_graphic_level()
664 smu7_get_sleep_divider_id_from_clock(engine_clock, in tonga_populate_single_graphic_level()
1459 uint32_t engine_clock, in tonga_populate_memory_timing_parameters() argument
[all …]
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| D | ci_smumgr.c | 1622 uint32_t engine_clock, in ci_populate_memory_timing_parameters() argument
1633 engine_clock, memory_clock); in ci_populate_memory_timing_parameters()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/ |
| D | si_dpm.c | 1830 u32 engine_clock,
4718 u32 engine_clock) in si_calculate_memory_refresh_rate() argument
4731 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; in si_calculate_memory_refresh_rate()
5224 u32 engine_clock, in si_calculate_sclk_params() argument
5243 engine_clock, false, ÷rs); in si_calculate_sclk_params()
5249 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in si_calculate_sclk_params()
5266 u32 vco_freq = engine_clock * dividers.post_div; in si_calculate_sclk_params()
5282 sclk->sclk_value = engine_clock; in si_calculate_sclk_params()
5294 u32 engine_clock, in si_populate_sclk_value() argument
5300 ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp); in si_populate_sclk_value()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/inc/ |
| D | amdgpu_smu.h | 323 uint32_t engine_clock; member
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