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Searched refs:event_base (Results 1 – 24 of 24) sorted by relevance

/kernel/linux/linux-5.10/drivers/clocksource/
Dtimer-qcom.c34 static void __iomem *event_base; variable
42 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); in msm_timer_interrupt()
44 writel_relaxed(ctrl, event_base + TIMER_ENABLE); in msm_timer_interrupt()
53 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); in msm_timer_set_next_event()
56 writel_relaxed(ctrl, event_base + TIMER_ENABLE); in msm_timer_set_next_event()
58 writel_relaxed(ctrl, event_base + TIMER_CLEAR); in msm_timer_set_next_event()
59 writel_relaxed(cycles, event_base + TIMER_MATCH_VAL); in msm_timer_set_next_event()
65 writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE); in msm_timer_set_next_event()
73 ctrl = readl_relaxed(event_base + TIMER_ENABLE); in msm_timer_shutdown()
75 writel_relaxed(ctrl, event_base + TIMER_ENABLE); in msm_timer_shutdown()
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/kernel/linux/linux-5.10/arch/x86/events/
Dmsr.c211 event->hw.event_base = msr[cfg].msr; in msr_event_init()
221 if (event->hw.event_base) in msr_read_counter()
222 rdmsrl(event->hw.event_base, now); in msr_read_counter()
243 if (unlikely(event->hw.event_base == MSR_SMI_COUNT)) { in msr_event_update()
246 } else if (unlikely(event->hw.event_base == MSR_IA32_THERM_STATUS)) { in msr_event_update()
Drapl.c156 rdmsrl(event->hw.event_base, raw); in rapl_read_counter()
184 rdmsrl(event->hw.event_base, new_raw_count); in rapl_event_update()
368 event->hw.event_base = rapl_msrs[bit].msr; in rapl_pmu_event_init()
Dcore.c107 if (unlikely(!hwc->event_base)) in x86_perf_event_update()
1182 hwc->event_base = 0; in x86_assign_hw_event()
1191 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + in x86_assign_hw_event()
1199 hwc->event_base = x86_pmu_event_addr(hwc->idx); in x86_assign_hw_event()
1322 if (unlikely(!hwc->event_base)) in x86_perf_event_set_period()
1365 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); in x86_perf_event_set_period()
1380 wrmsrl(hwc->event_base, in x86_perf_event_set_period()
/kernel/linux/linux-5.10/drivers/perf/
Dthunderx2_pmu.c334 hwc->event_base = (unsigned long)tx2_pmu->base in init_cntr_base_l3c()
350 hwc->event_base = (unsigned long)tx2_pmu->base in init_cntr_base_dmc()
364 hwc->event_base = (unsigned long)tx2_pmu->base; in init_cntr_base_ccpi2()
380 reg_writel(0, hwc->event_base); in uncore_start_event_l3c()
410 reg_writel(0, hwc->event_base); in uncore_start_event_dmc()
451 hwc->event_base + CCPI2_PERF_CTL); in uncore_start_event_ccpi2()
460 reg_writel(0, hwc->event_base + CCPI2_PERF_CTL); in uncore_stop_event_ccpi2()
480 hwc->event_base + CCPI2_COUNTER_SEL); in tx2_uncore_event_update()
481 new = reg_readl(hwc->event_base + CCPI2_COUNTER_DATA_H); in tx2_uncore_event_update()
483 reg_readl(hwc->event_base + CCPI2_COUNTER_DATA_L); in tx2_uncore_event_update()
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Darm-ccn.c907 dt_cfg = hw->event_base; in arm_ccn_pmu_xp_dt_config()
961 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(wp); in arm_ccn_pmu_xp_watchpoint_config()
1004 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(hw->config_base); in arm_ccn_pmu_xp_event_config()
1027 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(port, in arm_ccn_pmu_node_event_config()
Darm_pmu.c461 hwc->event_base = 0; in __hw_perf_event_init()
Darm-cci.c1302 hwc->event_base = 0; in __hw_perf_event_init()
/kernel/linux/linux-5.10/arch/alpha/kernel/
Dperf_event.c351 evtype[n] = group->hw.event_base; in collect_events()
359 evtype[n] = pe->hw.event_base; in collect_events()
459 cpuc->evtype[n0] = event->hw.event_base; in alpha_pmu_add()
642 hwc->event_base = ev; in __hw_perf_event_init()
656 evtypes[n] = hwc->event_base; in __hw_perf_event_init()
/kernel/linux/linux-5.10/arch/s390/include/asm/
Dperf_event.h71 #define SAMPL_RATE(hwc) ((hwc)->event_base)
/kernel/linux/linux-5.10/arch/x86/events/intel/
Dcstate.c325 event->hw.event_base = core_msr[cfg].msr; in cstate_pmu_event_init()
334 event->hw.event_base = pkg_msr[cfg].msr; in cstate_pmu_event_init()
354 rdmsrl(event->hw.event_base, val); in cstate_pmu_read_counter()
Duncore.c120 rdmsrl(event->hw.event_base, count); in uncore_msr_read_counter()
137 if (!uncore_mmio_is_valid_offset(box, event->hw.event_base)) in uncore_mmio_read_counter()
140 return readq(box->io_addr + event->hw.event_base); in uncore_mmio_read_counter()
229 hwc->event_base = uncore_fixed_ctr(box); in uncore_assign_hw_event()
235 hwc->event_base = uncore_perf_ctr(box, hwc->idx); in uncore_assign_hw_event()
763 event->hw.event_base = uncore_freerunning_counter(box, event); in uncore_pmu_event_init()
Duncore_snb.c616 event->hw.event_base = base; in snb_uncore_imc_event_init()
Dp4.c874 rdmsrl(hwc->event_base, v); in p4_pmu_clear_cccr_ovf()
Duncore_snbep.c575 pci_read_config_dword(pdev, hwc->event_base, (u32 *)&count); in snbep_uncore_pci_read_counter()
576 pci_read_config_dword(pdev, hwc->event_base + 4, (u32 *)&count + 1); in snbep_uncore_pci_read_counter()
Dcore.c2541 wrmsrl(event->hw.event_base, 0); in intel_pmu_save_and_restart()
/kernel/linux/linux-5.10/arch/mips/kernel/
Dperf_event_mipsxx.c325 cntr_mask = (hwc->event_base >> 10) & 0xffff; in mipsxx_pmu_alloc_counter()
327 cntr_mask = (hwc->event_base >> 8) & 0xffff; in mipsxx_pmu_alloc_counter()
352 unsigned int range = evt->event_base >> 24; in mipsxx_pmu_enable_event()
357 cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0x3ff) | in mipsxx_pmu_enable_event()
362 cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) | in mipsxx_pmu_enable_event()
440 M_PERFCTL_EVENT(hwc->event_base & 0x3ff)); in mipspmu_event_set_period()
1572 hwc->event_base = mipspmu_perf_event_encode(pev); in __hw_perf_event_init()
/kernel/linux/linux-5.10/arch/sparc/kernel/
Dperf_event.c1356 events[n] = group->hw.event_base; in collect_events()
1365 events[n] = event->hw.event_base; in collect_events()
1385 cpuc->events[n0] = event->hw.event_base; in sparc_pmu_add()
1455 hwc->event_base = perf_event_encode(pmap); in sparc_pmu_event_init()
1461 hwc->event_base = attr->config; in sparc_pmu_event_init()
1481 events[n] = hwc->event_base; in sparc_pmu_event_init()
/kernel/linux/linux-5.10/drivers/fpga/
Ddfl-fme-perf.c788 struct fme_perf_event_ops *ops = get_event_ops(event->hw.event_base); in fme_perf_event_destroy()
826 hwc->event_base = evtype; in fme_perf_event_init()
844 struct fme_perf_event_ops *ops = get_event_ops(event->hw.event_base); in fme_perf_event_update()
858 struct fme_perf_event_ops *ops = get_event_ops(event->hw.event_base); in fme_perf_event_start()
/kernel/linux/linux-5.10/arch/x86/events/amd/
Duncore.c106 wrmsrl(hwc->event_base, (u64)local64_read(&hwc->prev_count)); in amd_uncore_start()
157 hwc->event_base = uncore->msr_base + 1 + (2 * hwc->idx); in amd_uncore_add()
/kernel/linux/linux-5.10/arch/powerpc/perf/
Dimc-pmu.c548 event->hw.event_base = (u64)pcni->vbase + l_config; in nest_imc_event_init()
884 event->hw.event_base = (u64)pcmi->vbase + (config & IMC_EVENT_OFFSET_MASK); in core_imc_event_init()
1033 return (u64 *)event->hw.event_base; in get_event_base_addr()
Dcore-book3s.c1528 flags[n] = group->hw.event_base; in collect_events()
1537 flags[n] = event->hw.event_base; in collect_events()
1570 cpuhw->flags[n0] = event->hw.event_base; in power_pmu_add()
2062 event->hw.event_base = cflags[n]; in power_pmu_event_init()
/kernel/linux/linux-5.10/include/linux/
Dperf_event.h141 unsigned long event_base; member
/kernel/linux/linux-5.10/arch/nds32/kernel/
Dperf_event_cpu.c819 hwc->event_base = 0; in __hw_perf_event_init()