Searched refs:gpu_offset (Results 1 – 10 of 10) sorted by relevance
1149 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()1221 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()1233 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()1245 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()1257 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()1281 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()1301 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()1505 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()1522 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()1563 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()[all …]
1021 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()1083 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()1085 track->vgt_strmout_bo_mc[tmp] = reloc->gpu_offset; in r600_cs_check_reg()1104 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()1213 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()1244 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()1280 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()1283 track->cb_color_bo_mc[tmp] = reloc->gpu_offset; in r600_cs_check_reg()1294 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()1296 track->db_bo_mc = reloc->gpu_offset; in r600_cs_check_reg()[all …]
191 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r200_packet0_check()204 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r200_packet0_check()228 ib[idx] = tmp + ((u32)reloc->gpu_offset); in r200_packet0_check()230 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r200_packet0_check()274 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r200_packet0_check()368 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r200_packet0_check()
679 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()692 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()721 ((idx_value & ~31) + (u32)reloc->gpu_offset); in r300_packet0_check()730 tmp = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()1091 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()1136 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()1201 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); in r300_packet3_check()
1280 tmp += (((u32)reloc->gpu_offset) >> 10); in r100_reloc_pitch_offset()1331 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); in r100_packet3_load_vbpntr()1343 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset); in r100_packet3_load_vbpntr()1357 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); in r100_packet3_load_vbpntr()1598 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()1611 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()1632 ib[idx] = tmp + ((u32)reloc->gpu_offset); in r100_packet0_check()1634 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()1652 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()1670 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()[all …]
593 lobj->gpu_offset = radeon_bo_gpu_offset(bo); in radeon_bo_list_validate()598 lobj->gpu_offset = radeon_bo_gpu_offset(lobj->robj); in radeon_bo_list_validate()
877 (*cs_reloc)->gpu_offset = in radeon_cs_packet_next_reloc()879 (*cs_reloc)->gpu_offset |= relocs_chunk->kdata[idx + 0]; in radeon_cs_packet_next_reloc()
489 start = reloc->gpu_offset; in radeon_vce_cs_reloc()
592 start = reloc->gpu_offset; in radeon_uvd_cs_reloc()
467 uint64_t gpu_offset; member