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Searched refs:i915_ggtt_offset (Results 1 – 25 of 25) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
Dintel_dsb.c224 i915_ggtt_offset(dsb->vma)); in intel_dsb_commit()
238 i915_ggtt_offset(dsb->vma), tail); in intel_dsb_commit()
240 i915_ggtt_offset(dsb->vma) + tail); in intel_dsb_commit()
Dintel_overlay.c819 iowrite32(i915_ggtt_offset(vma) + params->offset_Y, &regs->OBUF_0Y); in intel_overlay_do_put_image()
836 iowrite32(i915_ggtt_offset(vma) + params->offset_U, in intel_overlay_do_put_image()
838 iowrite32(i915_ggtt_offset(vma) + params->offset_V, in intel_overlay_do_put_image()
1332 overlay->flip_addr = i915_ggtt_offset(vma); in get_registers()
Dintel_fbdev.c266 i915_ggtt_offset(vma)); in intelfb_create()
Dintel_display_types.h1726 return i915_ggtt_offset(state->vma); in intel_plane_ggtt_offset()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gem/selftests/
Di915_gem_coherency.c227 *cs++ = lower_32_bits(i915_ggtt_offset(vma) + offset); in gpu_set()
228 *cs++ = upper_32_bits(i915_ggtt_offset(vma) + offset); in gpu_set()
233 *cs++ = i915_ggtt_offset(vma) + offset; in gpu_set()
237 *cs++ = i915_ggtt_offset(vma) + offset; in gpu_set()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/selftests/
Di915_perf.c239 i915_ggtt_offset(stream->noa_wait), 0, in live_noa_delay()
346 i915_ggtt_offset(stream->noa_wait), 0, in live_noa_gpr()
372 *cs++ = i915_ggtt_offset(rq->engine->status_page.vma) + in live_noa_gpr()
Di915_request.c1619 return (i915_ggtt_offset(ce->engine->status_page.vma) + in hwsp_offset()
1849 i915_ggtt_offset(engine->status_page.vma) + in plug()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/
Dintel_context_sseu.c27 offset = i915_ggtt_offset(ce->state) + in gen8_emit_rpcs_config()
Dintel_gt.h60 return i915_ggtt_offset(gt->scratch) + field; in intel_gt_scratch_offset()
Dintel_ring_submission.c154 set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma)); in ring_setup_status_page()
273 ENGINE_WRITE(engine, RING_START, i915_ggtt_offset(ring->vma)); in xcs_resume()
302 i915_ggtt_offset(ring->vma)); in xcs_resume()
726 *cs++ = i915_ggtt_offset(engine->kernel_context->state) | in mi_set_context()
733 *cs++ = i915_ggtt_offset(ce->state) | flags; in mi_set_context()
Dselftest_mocs.c250 offset = i915_ggtt_offset(vma); in check_mocs_engine()
255 offset -= i915_ggtt_offset(vma); in check_mocs_engine()
Dselftest_lrc.c841 *cs++ = i915_ggtt_offset(vma) + 4 * idx; in emit_semaphore_chain()
846 *cs++ = i915_ggtt_offset(vma) + 4 * (idx - 1); in emit_semaphore_chain()
915 *cs++ = i915_ggtt_offset(vma) + 4 * (idx - 1); in release_queue()
1057 i915_ggtt_offset(ce->engine->status_page.vma) + in create_rewinder()
1624 *cs++ = i915_ggtt_offset(vma); in live_busywait_preempt()
1635 *cs++ = i915_ggtt_offset(vma); in live_busywait_preempt()
1674 *cs++ = i915_ggtt_offset(vma); in live_busywait_preempt()
3190 *cs++ = i915_ggtt_offset(global); in preempt_user()
4214 *cs++ = i915_ggtt_offset(scratch) + n * sizeof(u32); in preserved_virtual_engine()
4712 i915_ggtt_offset(ce->engine->status_page.vma) + in emit_semaphore_signal()
[all …]
Dintel_renderstate.c107 so->batch_offset = i915_ggtt_offset(so->vma); in render_state_setup()
Dintel_timeline.c348 i915_ggtt_offset(tl->hwsp_ggtt) + in intel_timeline_pin()
524 tl->hwsp_offset += i915_ggtt_offset(vma); in __intel_timeline_get_seqno()
Dintel_lrc.c391 return (i915_ggtt_offset(engine->status_page.vma) + in intel_hws_preempt_address()
585 return i915_ggtt_offset(ce->state) | desc; in lrc_descriptor()
1226 if (regs[CTX_RING_START] != i915_ggtt_offset(ring->vma)) { in execlists_check_context()
1230 i915_ggtt_offset(ring->vma)); in execlists_check_context()
1231 regs[CTX_RING_START] = i915_ggtt_offset(ring->vma); in execlists_check_context()
2704 i915_ggtt_offset(rq->ring->vma), in process_csb()
3340 *cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET + in gen12_emit_timestamp_wa()
3368 *cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET + in gen12_emit_restore_scratch()
3384 *cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET + in gen12_emit_cmd_buf_wa()
3448 i915_ggtt_offset(ce->state) + in setup_indirect_ctx_bb()
[all …]
Dintel_context.c262 i915_ggtt_offset(ce->ring->vma), in __intel_context_do_pin_ww()
Dintel_engine_cs.c1370 i915_ggtt_offset(rq->ring->vma), in print_ring()
1662 i915_ggtt_offset(rq->ring->vma)); in intel_engine_dump()
1747 return ring == i915_ggtt_offset(rq->ring->vma); in match_ring()
Dgen6_ppgtt.c309 u32 ggtt_offset = i915_ggtt_offset(vma) / I915_GTT_PAGE_SIZE; in pd_vma_bind()
Dselftest_workarounds.c160 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i; in read_nonprivs()
Dintel_workarounds.c2099 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i; in wa_list_srm()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
Di915_perf.c463 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in oa_buffer_check_unlocked()
652 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in gen8_append_oa_reports()
949 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in gen7_append_oa_reports()
1260 stream->specific_ctx_id = i915_ggtt_offset(ce->state); in oa_get_render_ctx_id()
1402 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in gen7_init_oa_buffer()
1448 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in gen8_init_oa_buffer()
1502 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in gen12_init_oa_buffer()
1738 *cs++ = i915_ggtt_offset(vma) + (ts0 - batch) * 4; in alloc_noa_wait()
1775 *cs++ = i915_ggtt_offset(vma) + (jump - batch) * 4; in alloc_noa_wait()
1884 *cs++ = i915_ggtt_offset(stream->noa_wait); in alloc_oa_config_buffer()
[all …]
Di915_vma.h113 static inline u32 i915_ggtt_offset(const struct i915_vma *vma) in i915_ggtt_offset() function
Di915_gem.c398 node.start = i915_ggtt_offset(vma); in i915_gem_gtt_pread()
603 node.start = i915_ggtt_offset(vma); in i915_gem_gtt_pwrite_fast()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/uc/
Dintel_guc.h120 u32 offset = i915_ggtt_offset(vma); in intel_guc_ggtt_offset()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gvt/
Dscheduler.c539 bb->bb_start_cmd_va[1] = i915_ggtt_offset(bb->vma); in prepare_shadow_batch_buffer()
595 wa_ctx->indirect_ctx.shadow_gma = i915_ggtt_offset(vma); in prepare_shadow_wa_ctx()