/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
D | navi10_ih.c | 61 u32 ih_cntl, ih_rb_cntl; in force_update_wptr_for_self_int() local 67 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); in force_update_wptr_for_self_int() 73 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, in force_update_wptr_for_self_int() 76 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); in force_update_wptr_for_self_int() 77 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); in force_update_wptr_for_self_int() 78 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, in force_update_wptr_for_self_int() 80 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); in force_update_wptr_for_self_int() 93 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); in navi10_ih_enable_interrupts() local 95 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in navi10_ih_enable_interrupts() 96 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); in navi10_ih_enable_interrupts() [all …]
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D | vega10_ih.c | 49 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); in vega10_ih_enable_interrupts() local 51 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in vega10_ih_enable_interrupts() 52 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); in vega10_ih_enable_interrupts() 54 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { in vega10_ih_enable_interrupts() 59 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); in vega10_ih_enable_interrupts() 64 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); in vega10_ih_enable_interrupts() 65 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, in vega10_ih_enable_interrupts() 69 ih_rb_cntl)) { in vega10_ih_enable_interrupts() 74 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); in vega10_ih_enable_interrupts() 80 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); in vega10_ih_enable_interrupts() [all …]
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D | tonga_ih.c | 62 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in tonga_ih_enable_interrupts() local 64 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in tonga_ih_enable_interrupts() 65 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); in tonga_ih_enable_interrupts() 66 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in tonga_ih_enable_interrupts() 79 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in tonga_ih_disable_interrupts() local 81 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in tonga_ih_disable_interrupts() 82 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); in tonga_ih_disable_interrupts() 83 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in tonga_ih_disable_interrupts() 104 u32 interrupt_cntl, ih_rb_cntl, ih_doorbell_rtpr; in tonga_ih_irq_init() local 126 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in tonga_ih_irq_init() [all …]
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D | cz_ih.c | 63 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cz_ih_enable_interrupts() local 66 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in cz_ih_enable_interrupts() 68 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in cz_ih_enable_interrupts() 81 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cz_ih_disable_interrupts() local 84 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in cz_ih_disable_interrupts() 86 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in cz_ih_disable_interrupts() 109 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in cz_ih_irq_init() local 130 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); in cz_ih_irq_init() 131 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in cz_ih_irq_init() 132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in cz_ih_irq_init() [all …]
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D | iceland_ih.c | 63 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in iceland_ih_enable_interrupts() local 66 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in iceland_ih_enable_interrupts() 68 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in iceland_ih_enable_interrupts() 81 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in iceland_ih_disable_interrupts() local 84 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in iceland_ih_disable_interrupts() 86 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in iceland_ih_disable_interrupts() 110 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in iceland_ih_irq_init() local 130 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); in iceland_ih_irq_init() 131 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in iceland_ih_irq_init() 132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in iceland_ih_irq_init() [all …]
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D | cik_ih.c | 63 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cik_ih_enable_interrupts() local 66 ih_rb_cntl |= IH_RB_CNTL__RB_ENABLE_MASK; in cik_ih_enable_interrupts() 68 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in cik_ih_enable_interrupts() 81 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cik_ih_disable_interrupts() local 84 ih_rb_cntl &= ~IH_RB_CNTL__RB_ENABLE_MASK; in cik_ih_disable_interrupts() 86 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in cik_ih_disable_interrupts() 110 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in cik_ih_irq_init() local 129 ih_rb_cntl = (IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK | in cik_ih_irq_init() 133 ih_rb_cntl |= IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK; in cik_ih_irq_init() 139 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in cik_ih_irq_init()
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D | si_ih.c | 38 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_ih_enable_interrupts() local 41 ih_rb_cntl |= IH_RB_ENABLE; in si_ih_enable_interrupts() 43 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_ih_enable_interrupts() 49 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_ih_disable_interrupts() local 52 ih_rb_cntl &= ~IH_RB_ENABLE; in si_ih_disable_interrupts() 54 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_ih_disable_interrupts() 66 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in si_ih_irq_init() local 79 ih_rb_cntl = IH_WPTR_OVERFLOW_ENABLE | in si_ih_irq_init() 86 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_ih_irq_init()
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/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
D | r600.c | 3596 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in r600_enable_interrupts() local 3599 ih_rb_cntl |= IH_RB_ENABLE; in r600_enable_interrupts() 3601 WREG32(IH_RB_CNTL, ih_rb_cntl); in r600_enable_interrupts() 3607 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in r600_disable_interrupts() local 3610 ih_rb_cntl &= ~IH_RB_ENABLE; in r600_disable_interrupts() 3612 WREG32(IH_RB_CNTL, ih_rb_cntl); in r600_disable_interrupts() 3678 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in r600_irq_init() local 3713 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | in r600_irq_init() 3718 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; in r600_irq_init() 3724 WREG32(IH_RB_CNTL, ih_rb_cntl); in r600_irq_init()
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D | si.c | 5923 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_enable_interrupts() local 5926 ih_rb_cntl |= IH_RB_ENABLE; in si_enable_interrupts() 5928 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_enable_interrupts() 5934 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_disable_interrupts() local 5937 ih_rb_cntl &= ~IH_RB_ENABLE; in si_disable_interrupts() 5939 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_disable_interrupts() 5982 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in si_irq_init() local 6014 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | in si_irq_init() 6019 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; in si_irq_init() 6025 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_irq_init()
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D | cik.c | 6826 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in cik_enable_interrupts() local 6829 ih_rb_cntl |= IH_RB_ENABLE; in cik_enable_interrupts() 6831 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_enable_interrupts() 6844 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in cik_disable_interrupts() local 6847 ih_rb_cntl &= ~IH_RB_ENABLE; in cik_disable_interrupts() 6849 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_disable_interrupts() 6950 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; in cik_irq_init() local 6982 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | in cik_irq_init() 6987 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; in cik_irq_init() 6993 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_irq_init()
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