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Searched refs:io_base (Results 1 – 25 of 165) sorted by relevance

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/kernel/linux/linux-5.10/drivers/staging/vt6655/
Dmac.c62 void __iomem *io_base = priv->PortOffset; in MACbIsRegBitsOff() local
64 return !(ioread8(io_base + byRegOfs) & byTestBits); in MACbIsRegBitsOff()
82 void __iomem *io_base = priv->PortOffset; in MACbIsIntDisable() local
84 if (ioread32(io_base + MAC_REG_IMR)) in MACbIsIntDisable()
107 void __iomem *io_base = priv->PortOffset; in MACvSetShortRetryLimit() local
109 iowrite8(byRetryLimit, io_base + MAC_REG_SRT); in MACvSetShortRetryLimit()
129 void __iomem *io_base = priv->PortOffset; in MACvSetLongRetryLimit() local
131 iowrite8(byRetryLimit, io_base + MAC_REG_LRT); in MACvSetLongRetryLimit()
150 void __iomem *io_base = priv->PortOffset; in MACvSetLoopbackMode() local
154 iowrite8((ioread8(io_base + MAC_REG_TEST) & 0x3f) | byLoopbackMode, in MACvSetLoopbackMode()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/meson/
Dmeson_viu.c86 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1)); in meson_viu_set_g12a_osd1_matrix()
88 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2)); in meson_viu_set_g12a_osd1_matrix()
90 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF00_01)); in meson_viu_set_g12a_osd1_matrix()
92 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF02_10)); in meson_viu_set_g12a_osd1_matrix()
94 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF11_12)); in meson_viu_set_g12a_osd1_matrix()
96 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF20_21)); in meson_viu_set_g12a_osd1_matrix()
98 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF22)); in meson_viu_set_g12a_osd1_matrix()
101 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET0_1)); in meson_viu_set_g12a_osd1_matrix()
103 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET2)); in meson_viu_set_g12a_osd1_matrix()
106 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_EN_CTRL)); in meson_viu_set_g12a_osd1_matrix()
[all …]
Dmeson_crtc.c100 priv->io_base + _REG(VPP_PREBLEND_VD1_V_START_END)); in meson_g12a_crtc_atomic_enable()
105 priv->io_base + _REG(VPP_POSTBLEND_H_SIZE)); in meson_g12a_crtc_atomic_enable()
109 priv->io_base + _REG(VPP_OSD1_BLD_H_SCOPE)); in meson_g12a_crtc_atomic_enable()
112 priv->io_base + _REG(VPP_OSD1_BLD_V_SCOPE)); in meson_g12a_crtc_atomic_enable()
115 priv->io_base + _REG(VPP_OUT_H_V_SIZE)); in meson_g12a_crtc_atomic_enable()
136 priv->io_base + _REG(VPP_POSTBLEND_H_SIZE)); in meson_crtc_atomic_enable()
140 priv->io_base + _REG(VPP_PREBLEND_VD1_V_START_END)); in meson_crtc_atomic_enable()
143 priv->io_base + _REG(VPP_MISC)); in meson_crtc_atomic_enable()
192 priv->io_base + _REG(VPP_MISC)); in meson_crtc_atomic_disable()
246 priv->io_base + _REG(VPP_MISC)); in meson_crtc_enable_osd1()
[all …]
Dmeson_venc.c1044 priv->io_base + _REG(VENC_VDAC_SETTING)); in meson_venc_hdmi_mode_set()
1046 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); in meson_venc_hdmi_mode_set()
1047 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); in meson_venc_hdmi_mode_set()
1055 priv->io_base + _REG(ENCI_CFILT_CTRL)); in meson_venc_hdmi_mode_set()
1058 priv->io_base + _REG(ENCI_CFILT_CTRL2)); in meson_venc_hdmi_mode_set()
1061 writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING)); in meson_venc_hdmi_mode_set()
1064 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE)); in meson_venc_hdmi_mode_set()
1065 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV)); in meson_venc_hdmi_mode_set()
1069 priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN)); in meson_venc_hdmi_mode_set()
1071 priv->io_base + _REG(ENCI_SYNC_HSO_END)); in meson_venc_hdmi_mode_set()
[all …]
Dmeson_vpp.c38 writel(mux, priv->io_base + _REG(VPU_VIU_VENC_MUX_CTRL)); in meson_vpp_setup_mux()
60 priv->io_base + _REG(VPP_OSD_SCALE_COEF_IDX)); in meson_vpp_write_scaling_filter_coefs()
63 priv->io_base + _REG(VPP_OSD_SCALE_COEF)); in meson_vpp_write_scaling_filter_coefs()
85 priv->io_base + _REG(VPP_SCALE_COEF_IDX)); in meson_vpp_write_vd_scaling_filter_coefs()
88 priv->io_base + _REG(VPP_SCALE_COEF)); in meson_vpp_write_vd_scaling_filter_coefs()
95 writel_relaxed(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1)); in meson_vpp_init()
98 priv->io_base + _REG(VIU_MISC_CTRL1)); in meson_vpp_init()
100 priv->io_base + _REG(VPP_DOLBY_CTRL)); in meson_vpp_init()
102 priv->io_base + _REG(VPP_DUMMY_DATA1)); in meson_vpp_init()
104 writel_relaxed(0xf, priv->io_base + _REG(DOLBY_PATH_CTRL)); in meson_vpp_init()
[all …]
Dmeson_rdma.c39 priv->io_base + _REG(RDMA_CTRL)); in meson_rdma_init()
43 priv->io_base + _REG(RDMA_CTRL)); in meson_rdma_init()
68 priv->io_base + _REG(RDMA_ACCESS_AUTO)); in meson_rdma_setup()
75 priv->io_base + _REG(RDMA_CTRL)); in meson_rdma_stop()
81 priv->io_base + _REG(RDMA_ACCESS_AUTO)); in meson_rdma_stop()
113 writel_relaxed(val, priv->io_base + _REG(reg)); in meson_rdma_writel_sync()
122 priv->io_base + _REG(RDMA_AHB_START_ADDR_1)); in meson_rdma_flush()
126 priv->io_base + _REG(RDMA_AHB_END_ADDR_1)); in meson_rdma_flush()
132 priv->io_base + _REG(RDMA_ACCESS_AUTO)); in meson_rdma_flush()
Dmeson_osd_afbcd.c90 priv->io_base + _REG(VIU_SW_RESET)); in meson_gxm_afbcd_reset()
91 writel_relaxed(0, priv->io_base + _REG(VIU_SW_RESET)); in meson_gxm_afbcd_reset()
100 priv->io_base + _REG(OSD1_AFBCD_ENABLE)); in meson_gxm_afbcd_enable()
108 priv->io_base + _REG(OSD1_AFBCD_ENABLE)); in meson_gxm_afbcd_disable()
128 writel_relaxed(mode, priv->io_base + _REG(OSD1_AFBCD_MODE)); in meson_gxm_afbcd_setup()
134 priv->io_base + _REG(OSD1_AFBCD_SIZE_IN)); in meson_gxm_afbcd_setup()
137 priv->io_base + _REG(OSD1_AFBCD_HDR_PTR)); in meson_gxm_afbcd_setup()
139 priv->io_base + _REG(OSD1_AFBCD_FRAME_PTR)); in meson_gxm_afbcd_setup()
142 priv->io_base + _REG(OSD1_AFBCD_CHROMA_PTR)); in meson_gxm_afbcd_setup()
158 priv->io_base + _REG(OSD1_AFBCD_CONV_CTRL)); in meson_gxm_afbcd_setup()
[all …]
/kernel/linux/linux-5.10/arch/powerpc/platforms/embedded6xx/
Dflipper-pic.c48 void __iomem *io_base = irq_data_get_irq_chip_data(d); in flipper_pic_mask_and_ack() local
51 clrbits32(io_base + FLIPPER_IMR, mask); in flipper_pic_mask_and_ack()
53 out_be32(io_base + FLIPPER_ICR, mask); in flipper_pic_mask_and_ack()
59 void __iomem *io_base = irq_data_get_irq_chip_data(d); in flipper_pic_ack() local
62 out_be32(io_base + FLIPPER_ICR, 1 << irq); in flipper_pic_ack()
68 void __iomem *io_base = irq_data_get_irq_chip_data(d); in flipper_pic_mask() local
70 clrbits32(io_base + FLIPPER_IMR, 1 << irq); in flipper_pic_mask()
76 void __iomem *io_base = irq_data_get_irq_chip_data(d); in flipper_pic_unmask() local
78 setbits32(io_base + FLIPPER_IMR, 1 << irq); in flipper_pic_unmask()
115 static void __flipper_quiesce(void __iomem *io_base) in __flipper_quiesce() argument
[all …]
Dhlwd-pic.c45 void __iomem *io_base = irq_data_get_irq_chip_data(d); in hlwd_pic_mask_and_ack() local
48 clrbits32(io_base + HW_BROADWAY_IMR, mask); in hlwd_pic_mask_and_ack()
49 out_be32(io_base + HW_BROADWAY_ICR, mask); in hlwd_pic_mask_and_ack()
55 void __iomem *io_base = irq_data_get_irq_chip_data(d); in hlwd_pic_ack() local
57 out_be32(io_base + HW_BROADWAY_ICR, 1 << irq); in hlwd_pic_ack()
63 void __iomem *io_base = irq_data_get_irq_chip_data(d); in hlwd_pic_mask() local
65 clrbits32(io_base + HW_BROADWAY_IMR, 1 << irq); in hlwd_pic_mask()
71 void __iomem *io_base = irq_data_get_irq_chip_data(d); in hlwd_pic_unmask() local
73 setbits32(io_base + HW_BROADWAY_IMR, 1 << irq); in hlwd_pic_unmask()
76 clrbits32(io_base + HW_STARLET_IMR, 1 << irq); in hlwd_pic_unmask()
[all …]
/kernel/linux/linux-5.10/sound/isa/
Dsscape.c133 unsigned io_base; member
188 static inline void sscape_write_unsafe(unsigned io_base, enum GA_REG reg, in sscape_write_unsafe() argument
191 outb(reg, ODIE_ADDR_IO(io_base)); in sscape_write_unsafe()
192 outb(val, ODIE_DATA_IO(io_base)); in sscape_write_unsafe()
205 sscape_write_unsafe(s->io_base, reg, val); in sscape_write()
213 static inline unsigned char sscape_read_unsafe(unsigned io_base, in sscape_read_unsafe() argument
216 outb(reg, ODIE_ADDR_IO(io_base)); in sscape_read_unsafe()
217 return inb(ODIE_DATA_IO(io_base)); in sscape_read_unsafe()
223 static inline void set_host_mode_unsafe(unsigned io_base) in set_host_mode_unsafe() argument
225 outb(0x0, HOST_CTRL_IO(io_base)); in set_host_mode_unsafe()
[all …]
/kernel/linux/linux-5.10/drivers/watchdog/
Dni903x_wdt.c40 u16 io_base; member
58 u8 control = inb(wdt->io_base + NIWD_CONTROL); in ni903x_start()
60 outb(control | NIWD_CONTROL_RESET, wdt->io_base + NIWD_CONTROL); in ni903x_start()
61 outb(control | NIWD_CONTROL_PET, wdt->io_base + NIWD_CONTROL); in ni903x_start()
70 outb(((0x00FF0000 & counter) >> 16), wdt->io_base + NIWD_SEED2); in ni903x_wdd_set_timeout()
71 outb(((0x0000FF00 & counter) >> 8), wdt->io_base + NIWD_SEED1); in ni903x_wdd_set_timeout()
72 outb((0x000000FF & counter), wdt->io_base + NIWD_SEED0); in ni903x_wdd_set_timeout()
85 control = inb(wdt->io_base + NIWD_CONTROL); in ni903x_wdd_get_timeleft()
87 outb(control, wdt->io_base + NIWD_CONTROL); in ni903x_wdd_get_timeleft()
89 counter2 = inb(wdt->io_base + NIWD_COUNTER2); in ni903x_wdd_get_timeleft()
[all …]
Dnic7018_wdt.c46 u16 io_base; member
96 wdt->io_base + WDT_PRESET_PRESCALE); in nic7018_set_timeout()
111 control = inb(wdt->io_base + WDT_RELOAD_CTRL); in nic7018_start()
112 outb(control | WDT_RELOAD_PORT_EN, wdt->io_base + WDT_RELOAD_CTRL); in nic7018_start()
114 outb(1, wdt->io_base + WDT_RELOAD_PORT); in nic7018_start()
116 control = inb(wdt->io_base + WDT_CTRL); in nic7018_start()
117 outb(control | WDT_CTRL_RESET_EN, wdt->io_base + WDT_CTRL); in nic7018_start()
126 outb(0, wdt->io_base + WDT_CTRL); in nic7018_stop()
127 outb(0, wdt->io_base + WDT_RELOAD_CTRL); in nic7018_stop()
128 outb(0xF0, wdt->io_base + WDT_PRESET_PRESCALE); in nic7018_stop()
[all …]
/kernel/linux/linux-5.10/sound/soc/spear/
Dspdif_in.c38 void *io_base; member
52 writel(ctrl, host->io_base + SPDIF_IN_CTRL); in spdif_in_configure()
53 writel(0xF, host->io_base + SPDIF_IN_IRQ_MASK); in spdif_in_configure()
74 writel(0x0, host->io_base + SPDIF_IN_IRQ_MASK); in spdif_in_shutdown()
79 u32 ctrl = readl(host->io_base + SPDIF_IN_CTRL); in spdif_in_format()
91 writel(ctrl, host->io_base + SPDIF_IN_CTRL); in spdif_in_format()
128 ctrl = readl(host->io_base + SPDIF_IN_CTRL); in spdif_in_trigger()
130 writel(ctrl, host->io_base + SPDIF_IN_CTRL); in spdif_in_trigger()
131 writel(0xF, host->io_base + SPDIF_IN_IRQ_MASK); in spdif_in_trigger()
137 ctrl = readl(host->io_base + SPDIF_IN_CTRL); in spdif_in_trigger()
[all …]
Dspdif_out.c39 void __iomem *io_base; member
46 writel(SPDIF_OUT_RESET, host->io_base + SPDIF_OUT_SOFT_RST); in spdif_out_configure()
48 writel(readl(host->io_base + SPDIF_OUT_SOFT_RST) & ~SPDIF_OUT_RESET, in spdif_out_configure()
49 host->io_base + SPDIF_OUT_SOFT_RST); in spdif_out_configure()
54 host->io_base + SPDIF_OUT_CFG); in spdif_out_configure()
56 writel(0x7F, host->io_base + SPDIF_OUT_INT_STA_CLR); in spdif_out_configure()
57 writel(0x7F, host->io_base + SPDIF_OUT_INT_EN_CLR); in spdif_out_configure()
99 ctrl = readl(host->io_base + SPDIF_OUT_CTRL); in spdif_out_clock()
102 writel(ctrl, host->io_base + SPDIF_OUT_CTRL); in spdif_out_clock()
165 ctrl = readl(host->io_base + SPDIF_OUT_CTRL); in spdif_out_trigger()
[all …]
/kernel/linux/linux-5.10/drivers/fpga/
Dts73xx-fpga.c31 void __iomem *io_base; member
47 writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_init()
49 writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_init()
64 ret = readb_poll_timeout(priv->io_base + TS73XX_FPGA_CONFIG_REG, in ts73xx_fpga_write()
70 writeb(buf[i], priv->io_base + TS73XX_FPGA_DATA_REG); in ts73xx_fpga_write()
84 reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
86 writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
89 reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
91 writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
93 reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
[all …]
/kernel/linux/linux-5.10/drivers/hwspinlock/
Du8500_hsem.c90 void __iomem *io_base; in u8500_hsem_probe() local
97 io_base = devm_platform_ioremap_resource(pdev, 0); in u8500_hsem_probe()
98 if (IS_ERR(io_base)) in u8500_hsem_probe()
99 return PTR_ERR(io_base); in u8500_hsem_probe()
102 val = readl(io_base + HSEM_CTRL_REG); in u8500_hsem_probe()
103 writel((val & ~HSEM_PROTOCOL_1), io_base + HSEM_CTRL_REG); in u8500_hsem_probe()
106 writel(0xFFFF, io_base + HSEM_ICRALL); in u8500_hsem_probe()
116 hwlock->priv = io_base + HSEM_REGISTER_OFFSET + sizeof(u32) * i; in u8500_hsem_probe()
126 void __iomem *io_base = bank->lock[0].priv - HSEM_REGISTER_OFFSET; in u8500_hsem_remove() local
129 writel(0xFFFF, io_base + HSEM_ICRALL); in u8500_hsem_remove()
/kernel/linux/linux-5.10/drivers/crypto/hisilicon/sec2/
Dsec_main.c87 #define SEC_ADDR(qm, offset) ((qm)->io_base + (offset) + \
257 reg = readl_relaxed(qm->io_base + SEC_ENGINE_PF_CFG_OFF + in sec_get_endian()
306 qm->io_base + AM_CFG_SINGLE_PORT_MAX_TRANS); in sec_engine_init()
330 writel(AXUSER_BASE, qm->io_base + QM_ARUSER_M_CFG_1); in sec_set_user_domain_and_cache()
331 writel(ARUSER_M_CFG_ENABLE, qm->io_base + QM_ARUSER_M_CFG_ENABLE); in sec_set_user_domain_and_cache()
332 writel(AXUSER_BASE, qm->io_base + QM_AWUSER_M_CFG_1); in sec_set_user_domain_and_cache()
333 writel(AWUSER_M_CFG_ENABLE, qm->io_base + QM_AWUSER_M_CFG_ENABLE); in sec_set_user_domain_and_cache()
334 writel(WUSER_M_CFG_ENABLE, qm->io_base + QM_WUSER_M_CFG_ENABLE); in sec_set_user_domain_and_cache()
337 writel(AXI_M_CFG, qm->io_base + QM_AXI_M_CFG); in sec_set_user_domain_and_cache()
338 writel(AXI_M_CFG_ENABLE, qm->io_base + QM_AXI_M_CFG_ENABLE); in sec_set_user_domain_and_cache()
[all …]
/kernel/linux/linux-5.10/drivers/crypto/hisilicon/zip/
Dzip_main.c254 void __iomem *base = qm->io_base; in hisi_zip_set_user_domain_and_cache()
308 qm->io_base + HZIP_CORE_INT_MASK_REG); in hisi_zip_hw_error_enable()
314 writel(HZIP_CORE_INT_MASK_ALL, qm->io_base + HZIP_CORE_INT_SOURCE); in hisi_zip_hw_error_enable()
317 writel(0x1, qm->io_base + HZIP_CORE_INT_RAS_CE_ENB); in hisi_zip_hw_error_enable()
318 writel(0x0, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB); in hisi_zip_hw_error_enable()
320 qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); in hisi_zip_hw_error_enable()
323 writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG); in hisi_zip_hw_error_enable()
326 val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); in hisi_zip_hw_error_enable()
328 writel(val, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); in hisi_zip_hw_error_enable()
336 writel(HZIP_CORE_INT_MASK_ALL, qm->io_base + HZIP_CORE_INT_MASK_REG); in hisi_zip_hw_error_disable()
[all …]
/kernel/linux/linux-5.10/drivers/input/keyboard/
Dspear-keyboard.c57 void __iomem *io_base; member
76 sts = readl_relaxed(kbd->io_base + STATUS_REG); in spear_kbd_interrupt()
86 val = readl_relaxed(kbd->io_base + DATA_REG) & in spear_kbd_interrupt()
97 writel_relaxed(0, kbd->io_base + STATUS_REG); in spear_kbd_interrupt()
121 writel_relaxed(val, kbd->io_base + MODE_CTL_REG); in spear_kbd_open()
122 writel_relaxed(1, kbd->io_base + STATUS_REG); in spear_kbd_open()
125 val = readl_relaxed(kbd->io_base + MODE_CTL_REG); in spear_kbd_open()
127 writel_relaxed(val, kbd->io_base + MODE_CTL_REG); in spear_kbd_open()
138 val = readl_relaxed(kbd->io_base + MODE_CTL_REG); in spear_kbd_close()
140 writel_relaxed(val, kbd->io_base + MODE_CTL_REG); in spear_kbd_close()
[all …]
/kernel/linux/linux-5.10/drivers/mtd/nand/raw/
Dlpc32xx_slc.c221 void __iomem *io_base; member
243 writel(SLCCTRL_SW_RESET, SLC_CTRL(host->io_base)); in lpc32xx_nand_setup()
247 writel(0, SLC_CFG(host->io_base)); in lpc32xx_nand_setup()
248 writel(0, SLC_IEN(host->io_base)); in lpc32xx_nand_setup()
250 SLC_ICR(host->io_base)); in lpc32xx_nand_setup()
266 writel(tmp, SLC_TAC(host->io_base)); in lpc32xx_nand_setup()
279 tmp = readl(SLC_CFG(host->io_base)); in lpc32xx_nand_cmd_ctrl()
284 writel(tmp, SLC_CFG(host->io_base)); in lpc32xx_nand_cmd_ctrl()
288 writel(cmd, SLC_CMD(host->io_base)); in lpc32xx_nand_cmd_ctrl()
290 writel(cmd, SLC_ADDR(host->io_base)); in lpc32xx_nand_cmd_ctrl()
[all …]
Dlpc32xx_mlc.c181 void __iomem *io_base; member
237 writel(MLCCMD_RESET, MLC_CMD(host->io_base)); in lpc32xx_nand_setup()
247 writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base)); in lpc32xx_nand_setup()
251 writel(tmp, MLC_ICR(host->io_base)); in lpc32xx_nand_setup()
255 writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base)); in lpc32xx_nand_setup()
266 writel(tmp, MLC_TIME_REG(host->io_base)); in lpc32xx_nand_setup()
270 MLC_IRQ_MR(host->io_base)); in lpc32xx_nand_setup()
273 writel(MLCCEH_NORMAL, MLC_CEH(host->io_base)); in lpc32xx_nand_setup()
286 writel(cmd, MLC_CMD(host->io_base)); in lpc32xx_nand_cmd_ctrl()
288 writel(cmd, MLC_ADDR(host->io_base)); in lpc32xx_nand_cmd_ctrl()
[all …]
Dsocrates_nand.c27 void __iomem *io_base; member
44 out_be32(host->io_base, FPGA_NAND_ENABLE | in socrates_nand_write_buf()
65 out_be32(host->io_base, val); in socrates_nand_read_buf()
67 buf[i] = (in_be32(host->io_base) >> in socrates_nand_read_buf()
105 out_be32(host->io_base, val); in socrates_nand_cmd_ctrl()
115 if (in_be32(host->io_base) & FPGA_NAND_BUSY) in socrates_nand_device_ready()
148 host->io_base = of_iomap(ofdev->dev.of_node, 0); in socrates_nand_probe()
149 if (host->io_base == NULL) { in socrates_nand_probe()
197 iounmap(host->io_base); in socrates_nand_probe()
214 iounmap(host->io_base); in socrates_nand_remove()
/kernel/linux/linux-5.10/drivers/mtd/devices/
Dspear_smi.c174 void __iomem *io_base; member
229 ctrlreg1 = readl(dev->io_base + SMI_CR1); in spear_smi_read_sr()
231 writel(ctrlreg1 & ~(SW_MODE | WB_MODE), dev->io_base + SMI_CR1); in spear_smi_read_sr()
235 dev->io_base + SMI_CR2); in spear_smi_read_sr()
248 writel(ctrlreg1, dev->io_base + SMI_CR1); in spear_smi_read_sr()
249 writel(0, dev->io_base + SMI_CR2); in spear_smi_read_sr()
301 status = readl(dev->io_base + SMI_SR); in spear_smi_int_handler()
307 writel(0, dev->io_base + SMI_SR); in spear_smi_int_handler()
343 writel(0, dev->io_base + SMI_SR); in spear_smi_hw_init()
345 writel(val, dev->io_base + SMI_CR1); in spear_smi_hw_init()
[all …]
/kernel/linux/linux-5.10/drivers/mtd/spi-nor/controllers/
Dnxp-spifi.c57 void __iomem *io_base; member
69 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, in nxp_spifi_wait_for_cmd()
82 writel(SPIFI_STAT_RESET, spifi->io_base + SPIFI_STAT); in nxp_spifi_reset()
83 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, in nxp_spifi_reset()
115 writel(spifi->mcmd, spifi->io_base + SPIFI_MCMD); in nxp_spifi_set_memory_mode_on()
116 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, in nxp_spifi_set_memory_mode_on()
141 writel(cmd, spifi->io_base + SPIFI_CMD); in nxp_spifi_read_reg()
144 *buf++ = readb(spifi->io_base + SPIFI_DATA); in nxp_spifi_read_reg()
165 writel(cmd, spifi->io_base + SPIFI_CMD); in nxp_spifi_write_reg()
168 writeb(*buf++, spifi->io_base + SPIFI_DATA); in nxp_spifi_write_reg()
[all …]
/kernel/linux/linux-5.10/drivers/spi/
Dspi-stm32-qspi.c103 void __iomem *io_base; member
131 sr = readl_relaxed(qspi->io_base + QSPI_SR); in stm32_qspi_irq()
135 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_irq()
137 writel_relaxed(cr, qspi->io_base + QSPI_CR); in stm32_qspi_irq()
172 ret = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, in stm32_qspi_tx_poll()
180 tx_fifo(buf++, qspi->io_base + QSPI_DR); in stm32_qspi_tx_poll()
235 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_tx_dma()
247 writel_relaxed(cr | CR_DMAEN, qspi->io_base + QSPI_CR); in stm32_qspi_tx_dma()
258 writel_relaxed(cr & ~CR_DMAEN, qspi->io_base + QSPI_CR); in stm32_qspi_tx_dma()
284 return readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, sr, in stm32_qspi_wait_nobusy()
[all …]

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