Searched refs:max_backends_per_se (Results 1 – 19 of 19) sorted by relevance
910 rdev->config.cayman.max_backends_per_se = 4; in cayman_gpu_init()948 rdev->config.cayman.max_backends_per_se = 2; in cayman_gpu_init()962 rdev->config.cayman.max_backends_per_se = 2; in cayman_gpu_init()976 rdev->config.cayman.max_backends_per_se = 1; in cayman_gpu_init()983 rdev->config.cayman.max_backends_per_se = 1; in cayman_gpu_init()1104 …for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines)… in cayman_gpu_init()1108 …for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines)… in cayman_gpu_init()1138 if ((rdev->config.cayman.max_backends_per_se == 1) && in cayman_gpu_init()1150 rdev->config.cayman.max_backends_per_se * in cayman_gpu_init()
344 *value = rdev->config.cik.max_backends_per_se * in radeon_info_ioctl()347 *value = rdev->config.si.max_backends_per_se * in radeon_info_ioctl()350 *value = rdev->config.cayman.max_backends_per_se * in radeon_info_ioctl()
3108 rdev->config.si.max_backends_per_se = 4; in si_gpu_init()3125 rdev->config.si.max_backends_per_se = 4; in si_gpu_init()3143 rdev->config.si.max_backends_per_se = 4; in si_gpu_init()3160 rdev->config.si.max_backends_per_se = 2; in si_gpu_init()3177 rdev->config.si.max_backends_per_se = 1; in si_gpu_init()3294 rdev->config.si.max_backends_per_se); in si_gpu_init()
2100 unsigned max_backends_per_se; member2139 unsigned max_backends_per_se; member2170 unsigned max_backends_per_se; member
2339 u32 num_rbs = rdev->config.cik.max_backends_per_se * in cik_tiling_mode_table_init()3192 rdev->config.cik.max_backends_per_se = 2; in cik_gpu_init()3209 rdev->config.cik.max_backends_per_se = 4; in cik_gpu_init()3225 rdev->config.cik.max_backends_per_se = 2; in cik_gpu_init()3245 rdev->config.cik.max_backends_per_se = 1; in cik_gpu_init()3347 rdev->config.cik.max_backends_per_se); in cik_gpu_init()
399 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); in amdgpu_discovery_get_gfx_info()418 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); in amdgpu_discovery_get_gfx_info()
480 adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se; in amdgpu_atomfirmware_get_gfx_info()
1335 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/ in gfx_v6_0_get_rb_active_bitmap()1469 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v6_0_setup_rb()1488 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * in gfx_v6_0_setup_rb()1590 adev->gfx.config.max_backends_per_se = 4; in gfx_v6_0_constants_init()1607 adev->gfx.config.max_backends_per_se = 4; in gfx_v6_0_constants_init()1624 adev->gfx.config.max_backends_per_se = 4; in gfx_v6_0_constants_init()1641 adev->gfx.config.max_backends_per_se = 2; in gfx_v6_0_constants_init()1658 adev->gfx.config.max_backends_per_se = 1; in gfx_v6_0_constants_init()
145 unsigned max_backends_per_se; member
1631 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v7_0_get_rb_active_bitmap()1793 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v7_0_setup_rb()1811 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * in gfx_v7_0_setup_rb()4280 adev->gfx.config.max_backends_per_se = 2; in gfx_v7_0_gpu_early_init()4297 adev->gfx.config.max_backends_per_se = 4; in gfx_v7_0_gpu_early_init()4313 adev->gfx.config.max_backends_per_se = 2; in gfx_v7_0_gpu_early_init()4333 adev->gfx.config.max_backends_per_se = 1; in gfx_v7_0_gpu_early_init()
1698 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()1715 adev->gfx.config.max_backends_per_se = 4; in gfx_v8_0_gpu_early_init()1762 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()1778 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()1795 adev->gfx.config.max_backends_per_se = 1; in gfx_v8_0_gpu_early_init()1813 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()3469 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v8_0_get_rb_active_bitmap()3631 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v8_0_setup_rb()3649 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * in gfx_v8_0_setup_rb()
729 adev->gfx.config.max_backends_per_se = gfx_info->info.max_backends_per_se; in amdgpu_atombios_get_gfx_info()
713 config[no_regs++] = adev->gfx.config.max_backends_per_se; in amdgpu_debugfs_gca_config_read()
741 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * in amdgpu_info_ioctl()
2459 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v9_0_get_rb_active_bitmap()2470 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v9_0_setup_rb()
1859 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se); in amdgpu_device_parse_gpu_info_fw()
4584 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v10_0_get_rb_active_bitmap()4596 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v10_0_setup_rb()
1396 uint8_t max_backends_per_se; member1416 uint8_t max_backends_per_se; member1441 uint8_t max_backends_per_se; member
5654 UCHAR max_backends_per_se; member