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Searched refs:membase (Results 1 – 25 of 240) sorted by relevance

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/kernel/linux/linux-5.10/drivers/tty/serial/
Dmilbeaut_usio.c67 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE, in mlb_usio_stop_tx()
68 port->membase + MLB_USIO_REG_FCR); in mlb_usio_stop_tx()
69 writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_TBIE, in mlb_usio_stop_tx()
70 port->membase + MLB_USIO_REG_SCR); in mlb_usio_stop_tx()
78 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE, in mlb_usio_tx_chars()
79 port->membase + MLB_USIO_REG_FCR); in mlb_usio_tx_chars()
80 writeb(readb(port->membase + MLB_USIO_REG_SCR) & in mlb_usio_tx_chars()
82 port->membase + MLB_USIO_REG_SCR); in mlb_usio_tx_chars()
85 writew(port->x_char, port->membase + MLB_USIO_REG_DR); in mlb_usio_tx_chars()
96 (readw(port->membase + MLB_USIO_REG_FBYTE) & 0xff); in mlb_usio_tx_chars()
[all …]
Dxilinx_uartps.c231 while ((readl(port->membase + CDNS_UART_SR) & in cdns_uart_handle_rx()
234 rxbs_status = readl(port->membase + CDNS_UART_RXBS); in cdns_uart_handle_rx()
235 data = readl(port->membase + CDNS_UART_FIFO); in cdns_uart_handle_rx()
319 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR); in cdns_uart_handle_tx()
323 !(readl(port->membase + CDNS_UART_SR) & in cdns_uart_handle_tx()
332 port->membase + CDNS_UART_FIFO); in cdns_uart_handle_tx()
370 isrstatus = readl(port->membase + CDNS_UART_ISR); in cdns_uart_isr()
371 writel(isrstatus, port->membase + CDNS_UART_ISR); in cdns_uart_isr()
383 !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS)) in cdns_uart_isr()
472 mreg = readl(port->membase + CDNS_UART_MR); in cdns_uart_set_baud_rate()
[all …]
Dmcf.c62 return (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXEMPTY) ? in mcf_tx_empty()
73 sigs = (readb(port->membase + MCFUART_UIPR) & MCFUART_UIPR_CTS) ? in mcf_get_mctrl()
91 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1); in mcf_set_mctrl()
93 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP0); in mcf_set_mctrl()
104 writeb(MCFUART_UCR_TXENABLE, port->membase + MCFUART_UCR); in mcf_start_tx()
106 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1); in mcf_start_tx()
109 writeb(pp->imr, port->membase + MCFUART_UIMR); in mcf_start_tx()
119 writeb(pp->imr, port->membase + MCFUART_UIMR); in mcf_stop_tx()
129 writeb(pp->imr, port->membase + MCFUART_UIMR); in mcf_stop_rx()
140 writeb(MCFUART_UCR_CMDBREAKSTART, port->membase + MCFUART_UCR); in mcf_break_ctl()
[all …]
Dmvebu-uart.c164 st = readl(port->membase + UART_STAT); in mvebu_uart_tx_empty()
186 unsigned int ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
189 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
198 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port)); in mvebu_uart_start_tx()
203 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
205 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
212 ctl = readl(port->membase + UART_CTRL(port)); in mvebu_uart_stop_rx()
214 writel(ctl, port->membase + UART_CTRL(port)); in mvebu_uart_stop_rx()
216 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
218 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
[all …]
Dtimbuart.c42 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~RXFLAGS; in timbuart_stop_rx()
43 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_rx()
49 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~TXBAE; in timbuart_stop_tx()
50 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_tx()
64 u32 isr = ioread32(port->membase + TIMBUART_ISR); in timbuart_tx_empty()
72 u8 ctl = ioread8(port->membase + TIMBUART_CTRL) | in timbuart_flush_buffer()
75 iowrite8(ctl, port->membase + TIMBUART_CTRL); in timbuart_flush_buffer()
76 iowrite32(TXBF, port->membase + TIMBUART_ISR); in timbuart_flush_buffer()
84 while (ioread32(port->membase + TIMBUART_ISR) & RXDP) { in timbuart_rx_chars()
85 u8 ch = ioread8(port->membase + TIMBUART_RXFIFO); in timbuart_rx_chars()
[all …]
Dlpc32xx_hs.c103 port->membase))) == 0) in wait_for_xmit_empty()
117 port->membase))) < 32) in wait_for_xmit_ready()
128 writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase)); in lpc32xx_hsuart_console_putchar()
168 if (!port->membase) in lpc32xx_hsuart_console_setup()
247 while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) && in __serial_uart_flush()
249 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); in __serial_uart_flush()
258 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); in __serial_lpc32xx_rx()
266 LPC32XX_HSUART_IIR(port->membase)); in __serial_lpc32xx_rx()
274 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); in __serial_lpc32xx_rx()
288 writel((u32)port->x_char, LPC32XX_HSUART_FIFO(port->membase)); in __serial_lpc32xx_tx()
[all …]
Dqcom_geni_serial.c202 uport->membase = devm_platform_ioremap_resource(pdev, 0); in qcom_geni_serial_request_port()
203 if (IS_ERR(uport->membase)) in qcom_geni_serial_request_port()
204 return PTR_ERR(uport->membase); in qcom_geni_serial_request_port()
205 port->se.base = uport->membase; in qcom_geni_serial_request_port()
225 geni_ios = readl(uport->membase + SE_GENI_IOS); in qcom_geni_serial_get_mctrl()
247 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR); in qcom_geni_serial_set_mctrl()
296 reg = readl(uport->membase + offset); in qcom_geni_serial_poll_bit()
309 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN); in qcom_geni_serial_setup_tx()
311 writel(m_cmd, uport->membase + SE_GENI_M_CMD0); in qcom_geni_serial_setup_tx()
322 writel(M_GENI_CMD_ABORT, uport->membase + in qcom_geni_serial_poll_tx_done()
[all …]
Dmeson_uart.c96 val = readl(port->membase + AML_UART_STATUS); in meson_uart_tx_empty()
105 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_stop_tx()
107 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_stop_tx()
114 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_stop_rx()
116 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_stop_rx()
128 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_shutdown()
131 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_shutdown()
147 while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) { in meson_uart_start_tx()
149 writel(port->x_char, port->membase + AML_UART_WFIFO); in meson_uart_start_tx()
159 writel(ch, port->membase + AML_UART_WFIFO); in meson_uart_start_tx()
[all …]
Dfsl_linflexuart.c147 ier = readl(port->membase + LINIER); in linflex_stop_tx()
149 writel(ier, port->membase + LINIER); in linflex_stop_tx()
156 ier = readl(port->membase + LINIER); in linflex_stop_rx()
157 writel(ier & ~LINFLEXD_LINIER_DRIE, port->membase + LINIER); in linflex_stop_rx()
168 writeb(c, sport->membase + BDRL); in linflex_transmit_buffer()
171 while (((status = readl(sport->membase + UARTSR)) & in linflex_transmit_buffer()
180 sport->membase + UARTSR); in linflex_transmit_buffer()
195 ier = readl(port->membase + LINIER); in linflex_start_tx()
196 writel(ier | LINFLEXD_LINIER_DTIE, port->membase + LINIER); in linflex_start_tx()
209 writeb(sport->x_char, sport->membase + BDRL); in linflex_txint()
[all …]
Damba-pl010.c65 cr = readb(uap->port.membase + UART010_CR); in pl010_stop_tx()
67 writel(cr, uap->port.membase + UART010_CR); in pl010_stop_tx()
76 cr = readb(uap->port.membase + UART010_CR); in pl010_start_tx()
78 writel(cr, uap->port.membase + UART010_CR); in pl010_start_tx()
87 cr = readb(uap->port.membase + UART010_CR); in pl010_stop_rx()
89 writel(cr, uap->port.membase + UART010_CR); in pl010_stop_rx()
97 cr = readb(uap->port.membase + UART010_CR); in pl010_disable_ms()
99 writel(cr, uap->port.membase + UART010_CR); in pl010_disable_ms()
108 cr = readb(uap->port.membase + UART010_CR); in pl010_enable_ms()
110 writel(cr, uap->port.membase + UART010_CR); in pl010_enable_ms()
[all …]
Ddigicolor-usart.c85 return !!(readb_relaxed(port->membase + UA_STATUS_FIFO) & in digicolor_uart_tx_full()
91 return !!(readb_relaxed(port->membase + UA_STATUS_FIFO) & in digicolor_uart_rx_empty()
97 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); in digicolor_uart_stop_tx()
100 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); in digicolor_uart_stop_tx()
105 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); in digicolor_uart_start_tx()
108 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); in digicolor_uart_start_tx()
113 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); in digicolor_uart_stop_rx()
116 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); in digicolor_uart_stop_rx()
127 writeb_relaxed(UA_INT_RX, dp->port.membase + UA_INTFLAG_SET); in digicolor_rx_poll()
145 ch = readb_relaxed(port->membase + UA_EMI_REC); in digicolor_uart_rx()
[all …]
Dlantiq.c159 __raw_writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); in lqasc_stop_rx()
168 fifocnt = __raw_readl(port->membase + LTQ_ASC_FSTAT) & in lqasc_rx_chars()
172 ch = readb(port->membase + LTQ_ASC_RBUF); in lqasc_rx_chars()
173 rsr = (__raw_readl(port->membase + LTQ_ASC_STATE) in lqasc_rx_chars()
186 port->membase + LTQ_ASC_WHBSTATE); in lqasc_rx_chars()
190 port->membase + LTQ_ASC_WHBSTATE); in lqasc_rx_chars()
195 port->membase + LTQ_ASC_WHBSTATE); in lqasc_rx_chars()
233 while (((__raw_readl(port->membase + LTQ_ASC_FSTAT) & in lqasc_tx_chars()
236 writeb(port->x_char, port->membase + LTQ_ASC_TBUF); in lqasc_tx_chars()
246 port->membase + LTQ_ASC_TBUF); in lqasc_tx_chars()
[all …]
Dfsl_lpuart.c332 return readl(port->membase + off); in lpuart32_read()
334 return ioread32be(port->membase + off); in lpuart32_read()
345 writel(val, port->membase + off); in lpuart32_write()
348 iowrite32be(val, port->membase + off); in lpuart32_write()
390 temp = readb(port->membase + UARTCR2); in lpuart_stop_tx()
392 writeb(temp, port->membase + UARTCR2); in lpuart_stop_tx()
408 temp = readb(port->membase + UARTCR2); in lpuart_stop_rx()
409 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); in lpuart_stop_rx()
567 val = readb(sport->port.membase + UARTCFIFO); in lpuart_flush_buffer()
569 writeb(val, sport->port.membase + UARTCFIFO); in lpuart_flush_buffer()
[all …]
Daltera_jtaguart.c64 return (readl(port->membase + ALTERA_JTAGUART_CONTROL_REG) & in altera_jtaguart_tx_empty()
83 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG); in altera_jtaguart_start_tx()
92 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG); in altera_jtaguart_stop_tx()
101 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG); in altera_jtaguart_stop_rx()
123 while ((status = readl(port->membase + ALTERA_JTAGUART_DATA_REG)) & in altera_jtaguart_rx_chars()
147 writel(port->x_char, port->membase + ALTERA_JTAGUART_DATA_REG); in altera_jtaguart_tx_chars()
155 count = (readl(port->membase + ALTERA_JTAGUART_CONTROL_REG) & in altera_jtaguart_tx_chars()
164 port->membase + ALTERA_JTAGUART_DATA_REG); in altera_jtaguart_tx_chars()
175 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG); in altera_jtaguart_tx_chars()
186 isr = (readl(port->membase + ALTERA_JTAGUART_CONTROL_REG) >> in altera_jtaguart_interrupt()
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/allwinner/
Dsun4i-emac.c76 void __iomem *membase; member
98 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
102 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
111 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex()
115 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex()
193 writel(0, db->membase + EMAC_CTL_REG); in emac_reset()
195 writel(EMAC_CTL_RESET, db->membase + EMAC_CTL_REG); in emac_reset()
246 reg_val = readl(db->membase + EMAC_TX_MODE_REG); in emac_setup()
249 db->membase + EMAC_TX_MODE_REG); in emac_setup()
253 reg_val = readl(db->membase + EMAC_MAC_CTL0_REG); in emac_setup()
[all …]
/kernel/linux/linux-5.10/drivers/atm/
Didt77252.h355 void __iomem *membase; /* SAR's memory base address */ member
441 #define SAR_REG_DR0 (card->membase + 0x00)
442 #define SAR_REG_DR1 (card->membase + 0x04)
443 #define SAR_REG_DR2 (card->membase + 0x08)
444 #define SAR_REG_DR3 (card->membase + 0x0C)
445 #define SAR_REG_CMD (card->membase + 0x10)
446 #define SAR_REG_CFG (card->membase + 0x14)
447 #define SAR_REG_STAT (card->membase + 0x18)
448 #define SAR_REG_RSQB (card->membase + 0x1C)
449 #define SAR_REG_RSQT (card->membase + 0x20)
[all …]
/kernel/linux/linux-5.10/drivers/net/mdio/
Dmdio-ipq4019.c35 void __iomem *membase; member
43 return readl_poll_timeout(priv->membase + MDIO_CMD_REG, busy, in ipq4019_mdio_wait_busy()
63 data = readl(priv->membase + MDIO_MODE_REG); in ipq4019_mdio_read()
67 writel(data, priv->membase + MDIO_MODE_REG); in ipq4019_mdio_read()
70 writel((mii_id << 8) | mmd, priv->membase + MDIO_ADDR_REG); in ipq4019_mdio_read()
73 writel(reg, priv->membase + MDIO_DATA_WRITE_REG); in ipq4019_mdio_read()
78 data = readl(priv->membase + MDIO_MODE_REG); in ipq4019_mdio_read()
82 writel(data, priv->membase + MDIO_MODE_REG); in ipq4019_mdio_read()
85 writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG); in ipq4019_mdio_read()
91 writel(cmd, priv->membase + MDIO_CMD_REG); in ipq4019_mdio_read()
[all …]
Dmdio-sun4i.c32 void __iomem *membase; member
43 writel((mii_id << 8) | regnum, data->membase + EMAC_MAC_MADR_REG); in sun4i_mdio_read()
45 writel(0x1, data->membase + EMAC_MAC_MCMD_REG); in sun4i_mdio_read()
49 while (readl(data->membase + EMAC_MAC_MIND_REG) & 0x1) { in sun4i_mdio_read()
56 writel(0x0, data->membase + EMAC_MAC_MCMD_REG); in sun4i_mdio_read()
58 value = readl(data->membase + EMAC_MAC_MRDD_REG); in sun4i_mdio_read()
70 writel((mii_id << 8) | regnum, data->membase + EMAC_MAC_MADR_REG); in sun4i_mdio_write()
72 writel(0x1, data->membase + EMAC_MAC_MCMD_REG); in sun4i_mdio_write()
76 while (readl(data->membase + EMAC_MAC_MIND_REG) & 0x1) { in sun4i_mdio_write()
83 writel(0x0, data->membase + EMAC_MAC_MCMD_REG); in sun4i_mdio_write()
[all …]
/kernel/linux/linux-5.10/drivers/gpio/
Dgpio-timberdale.c35 void __iomem *membase; member
49 reg = ioread32(tgpio->membase + offset); in timbgpio_update_bit()
56 iowrite32(reg, tgpio->membase + offset); in timbgpio_update_bit()
72 value = ioread32(tgpio->membase + TGPIOVAL); in timbgpio_gpio_get()
109 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER); in timbgpio_irq_disable()
121 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER); in timbgpio_irq_enable()
137 ver = ioread32(tgpio->membase + TGPIO_VER); in timbgpio_irq_type()
141 lvr = ioread32(tgpio->membase + TGPIO_LVR); in timbgpio_irq_type()
142 flr = ioread32(tgpio->membase + TGPIO_FLR); in timbgpio_irq_type()
144 bflr = ioread32(tgpio->membase + TGPIO_BFLR); in timbgpio_irq_type()
[all …]
Dgpio-sa1100.c18 void __iomem *membase; member
41 return readl_relaxed(sa1100_gpio_chip(chip)->membase + R_GPLR) & in sa1100_gpio_get()
49 writel_relaxed(BIT(offset), sa1100_gpio_chip(chip)->membase + reg); in sa1100_gpio_set()
54 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR; in sa1100_get_direction()
64 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR; in sa1100_direction_input()
76 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR; in sa1100_direction_output()
104 .membase = (void *)&GPLR,
115 void *base = sgc->membase; in sa1100_update_edge_regs()
157 writel_relaxed(BIT(d->hwirq), sgc->membase + R_GEDR); in sa1100_gpio_ack()
233 void __iomem *gedr = sgc->membase + R_GEDR; in sa1100_gpio_handler()
[all …]
/kernel/linux/linux-5.10/drivers/i2c/busses/
Di2c-uniphier-f.c81 void __iomem *membase; member
109 writel(*priv->buf++, priv->membase + UNIPHIER_FI2C_DTTX); in uniphier_fi2c_fill_txfifo()
123 *priv->buf++ = readl(priv->membase + UNIPHIER_FI2C_DTRX); in uniphier_fi2c_drain_rxfifo()
130 writel(priv->enabled_irqs, priv->membase + UNIPHIER_FI2C_IE); in uniphier_fi2c_set_irqs()
136 writel(mask, priv->membase + UNIPHIER_FI2C_IC); in uniphier_fi2c_clear_irqs()
144 priv->membase + UNIPHIER_FI2C_CR); in uniphier_fi2c_stop()
154 irq_status = readl(priv->membase + UNIPHIER_FI2C_INT); in uniphier_fi2c_interrupt()
213 priv->membase + UNIPHIER_FI2C_CR); in uniphier_fi2c_interrupt()
254 writel(0, priv->membase + UNIPHIER_FI2C_TBC); in uniphier_fi2c_tx_init()
257 priv->membase + UNIPHIER_FI2C_DTTX); in uniphier_fi2c_tx_init()
[all …]
/kernel/linux/linux-5.10/drivers/reset/
Dreset-stm32mp1.c18 void __iomem *membase; member
36 addr = data->membase + (bank * reg_width); in stm32_reset_update()
66 reg = readl(data->membase + (bank * reg_width)); in stm32_reset_status()
86 void __iomem *membase; in stm32_reset_probe() local
94 membase = devm_ioremap_resource(dev, res); in stm32_reset_probe()
95 if (IS_ERR(membase)) in stm32_reset_probe()
96 return PTR_ERR(membase); in stm32_reset_probe()
98 data->membase = membase; in stm32_reset_probe()
/kernel/linux/linux-5.10/drivers/input/keyboard/
Dlocomokbd.c72 static inline void locomokbd_charge_all(unsigned long membase) in locomokbd_charge_all() argument
74 locomo_writel(0x00FF, membase + LOCOMO_KSC); in locomokbd_charge_all()
77 static inline void locomokbd_activate_all(unsigned long membase) in locomokbd_activate_all() argument
81 locomo_writel(0, membase + LOCOMO_KSC); in locomokbd_activate_all()
82 r = locomo_readl(membase + LOCOMO_KIC); in locomokbd_activate_all()
84 locomo_writel(r, membase + LOCOMO_KIC); in locomokbd_activate_all()
87 static inline void locomokbd_activate_col(unsigned long membase, int col) in locomokbd_activate_col() argument
94 locomo_writel(nbset, membase + LOCOMO_KSC); in locomokbd_activate_col()
97 static inline void locomokbd_reset_col(unsigned long membase, int col) in locomokbd_reset_col() argument
102 locomo_writel(nbset, membase + LOCOMO_KSC); in locomokbd_reset_col()
[all …]
/kernel/linux/linux-5.10/drivers/dma/
Dtimb_dma.c72 void __iomem *membase; member
89 void __iomem *membase; member
118 ier = ioread32(td->membase + TIMBDMA_IER); in __td_enable_chan_irq()
122 iowrite32(ier, td->membase + TIMBDMA_IER); in __td_enable_chan_irq()
136 isr = ioread32(td->membase + TIMBDMA_ISR) & (1 << id); in __td_dma_done_ack()
138 iowrite32(isr, td->membase + TIMBDMA_ISR); in __td_dma_done_ack()
193 td_chan, td_chan->chan.chan_id, td_chan->membase); in __td_start_dma()
198 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_RX_DHAR); in __td_start_dma()
199 iowrite32(td_desc->txd.phys, td_chan->membase + in __td_start_dma()
202 iowrite32(td_chan->bytes_per_line, td_chan->membase + in __td_start_dma()
[all …]
/kernel/linux/linux-5.10/drivers/clk/x86/
Dclk-cgu.c31 lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift, in lgm_clk_register_fixed()
51 val = lgm_get_clk_val(mux->membase, mux->reg, mux->shift, in lgm_clk_mux_get_parent()
68 lgm_set_clk_val(mux->membase, mux->reg, mux->shift, in lgm_clk_mux_set_parent()
113 mux->membase = ctx->membase; in lgm_clk_register_mux()
128 lgm_set_clk_val(mux->membase, reg, shift, width, list->mux_val); in lgm_clk_register_mux()
143 val = lgm_get_clk_val(divider->membase, divider->reg, in lgm_clk_divider_recalc_rate()
175 lgm_set_clk_val(divider->membase, divider->reg, in lgm_clk_divider_set_rate()
188 lgm_set_clk_val(div->membase, div->reg, div->shift_gate, in lgm_clk_divider_enable_disable()
238 div->membase = ctx->membase; in lgm_clk_register_divider()
256 lgm_set_clk_val(div->membase, reg, shift, width, list->div_val); in lgm_clk_register_divider()
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