| /kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
| D | rv740_dpm.c | 94 u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock) in rv740_get_dll_speed() argument
105 data_rate = (u16)(memory_clock * factor / 1000); in rv740_get_dll_speed()
187 u32 engine_clock, u32 memory_clock, in rv740_populate_mclk_value() argument
205 memory_clock, false, ÷rs); in rv740_populate_mclk_value()
247 u32 vco_freq = memory_clock * dividers.post_div; in rv740_populate_mclk_value()
266 memory_clock); in rv740_populate_mclk_value()
271 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in rv740_populate_mclk_value()
405 u8 rv740_get_mclk_frequency_ratio(u32 memory_clock) in rv740_get_mclk_frequency_ratio() argument
409 if ((memory_clock < 10000) || (memory_clock > 47500)) in rv740_get_mclk_frequency_ratio()
412 mc_para_index = (u8)((memory_clock - 10000) / 2500); in rv740_get_mclk_frequency_ratio()
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| D | rv770_dpm.h | 184 u32 engine_clock, u32 memory_clock,
205 u32 engine_clock, u32 memory_clock,
212 u8 rv740_get_mclk_frequency_ratio(u32 memory_clock);
213 u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock);
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| D | cypress_dpm.c | 475 u32 engine_clock, u32 memory_clock, in cypress_populate_mclk_value() argument
502 memory_clock, strobe_mode, ÷rs); in cypress_populate_mclk_value()
556 u32 vco_freq = memory_clock * dividers.post_div; in cypress_populate_mclk_value()
575 memory_clock); in cypress_populate_mclk_value()
598 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in cypress_populate_mclk_value()
612 u32 memory_clock, bool strobe_mode) in cypress_get_mclk_frequency_ratio() argument
618 if (memory_clock < 10000) in cypress_get_mclk_frequency_ratio()
620 else if (memory_clock > 47500) in cypress_get_mclk_frequency_ratio()
623 mc_para_index = (u8)((memory_clock - 10000) / 2500); in cypress_get_mclk_frequency_ratio()
625 if (memory_clock < 65000) in cypress_get_mclk_frequency_ratio()
[all …]
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| D | cypress_dpm.h | 125 u32 engine_clock, u32 memory_clock);
157 u32 memory_clock, bool strobe_mode);
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| D | rv730_dpm.c | 119 u32 engine_clock, u32 memory_clock, in rv730_populate_mclk_value() argument
135 memory_clock, false, ÷rs); in rv730_populate_mclk_value()
167 u32 vco_freq = memory_clock * post_divider; in rv730_populate_mclk_value()
187 mclk->mclk730.mclk_value = cpu_to_be32(memory_clock); in rv730_populate_mclk_value()
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| D | ci_dpm.c | 155 extern u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);
156 extern u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);
2482 const u32 memory_clock, in ci_register_patching_mc_arb() argument
2494 if ((memory_clock > 100000) && (memory_clock <= 125000)) { in ci_register_patching_mc_arb()
2498 } else if ((memory_clock > 125000) && (memory_clock <= 137500)) { in ci_register_patching_mc_arb()
2774 u32 memory_clock, in ci_calculate_mclk_params() argument
2792 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); in ci_calculate_mclk_params()
2819 freq_nom = memory_clock * 4 * (1 << mpll_param.post_div); in ci_calculate_mclk_params()
2821 freq_nom = memory_clock * 2 * (1 << mpll_param.post_div); in ci_calculate_mclk_params()
2846 mclk->MclkFrequency = memory_clock; in ci_calculate_mclk_params()
[all …]
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| D | rv770_dpm.c | 317 static void rv770_calculate_fractional_mpll_feedback_divider(u32 memory_clock, in rv770_calculate_fractional_mpll_feedback_divider() argument
328 fyclk = (memory_clock * 8) / 2; in rv770_calculate_fractional_mpll_feedback_divider()
330 fyclk = (memory_clock * 4) / 2; in rv770_calculate_fractional_mpll_feedback_divider()
386 u32 engine_clock, u32 memory_clock, in rv770_populate_mclk_value() argument
410 memory_clock, false, ÷rs); in rv770_populate_mclk_value()
417 rv770_calculate_fractional_mpll_feedback_divider(memory_clock, reference_clock, in rv770_populate_mclk_value()
444 rv770_calculate_fractional_mpll_feedback_divider(memory_clock, in rv770_populate_mclk_value()
472 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in rv770_populate_mclk_value()
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| D | si_dpm.c | 3807 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) in si_get_ddr3_mclk_frequency_ratio() argument
3811 if (memory_clock < 10000) in si_get_ddr3_mclk_frequency_ratio()
3813 else if (memory_clock >= 80000) in si_get_ddr3_mclk_frequency_ratio()
3816 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); in si_get_ddr3_mclk_frequency_ratio()
3820 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) in si_get_mclk_frequency_ratio() argument
3825 if (memory_clock < 12500) in si_get_mclk_frequency_ratio()
3827 else if (memory_clock > 47500) in si_get_mclk_frequency_ratio()
3830 mc_para_index = (u8)((memory_clock - 10000) / 2500); in si_get_mclk_frequency_ratio()
3832 if (memory_clock < 65000) in si_get_mclk_frequency_ratio()
3834 else if (memory_clock > 135000) in si_get_mclk_frequency_ratio()
[all …]
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| D | ni_dpm.c | 2161 u32 memory_clock, in ni_populate_mclk_value() argument
2183 memory_clock, strobe_mode, ÷rs); in ni_populate_mclk_value()
2237 u32 vco_freq = memory_clock * dividers.post_div; in ni_populate_mclk_value()
2256 memory_clock); in ni_populate_mclk_value()
2280 mclk->mclk_value = cpu_to_be32(memory_clock); in ni_populate_mclk_value()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| D | iceland_smumgr.c | 1046 uint32_t memory_clock, in iceland_calculate_mclk_params() argument
1068 memory_clock, &mpll_param, strobe_mode); in iceland_calculate_mclk_params()
1119 freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider); in iceland_calculate_mclk_params()
1121 freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider); in iceland_calculate_mclk_params()
1155 mclk->MclkFrequency = memory_clock; in iceland_calculate_mclk_params()
1169 static uint8_t iceland_get_mclk_frequency_ratio(uint32_t memory_clock, in iceland_get_mclk_frequency_ratio() argument
1175 if (memory_clock < 12500) { in iceland_get_mclk_frequency_ratio()
1177 } else if (memory_clock > 47500) { in iceland_get_mclk_frequency_ratio()
1180 mc_para_index = (uint8_t)((memory_clock - 10000) / 2500); in iceland_get_mclk_frequency_ratio()
1183 if (memory_clock < 65000) { in iceland_get_mclk_frequency_ratio()
[all …]
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| D | ci_smumgr.c | 1024 uint32_t memory_clock, in ci_calculate_mclk_params() argument
1045 memory_clock, &mpll_param, strobe_mode); in ci_calculate_mclk_params()
1077 freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider); in ci_calculate_mclk_params()
1079 freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider); in ci_calculate_mclk_params()
1104 mclk->MclkFrequency = memory_clock; in ci_calculate_mclk_params()
1118 static uint8_t ci_get_mclk_frequency_ratio(uint32_t memory_clock, in ci_get_mclk_frequency_ratio() argument
1124 if (memory_clock < 12500) in ci_get_mclk_frequency_ratio()
1126 else if (memory_clock > 47500) in ci_get_mclk_frequency_ratio()
1129 mc_para_index = (uint8_t)((memory_clock - 10000) / 2500); in ci_get_mclk_frequency_ratio()
1131 if (memory_clock < 65000) in ci_get_mclk_frequency_ratio()
[all …]
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| D | tonga_smumgr.c | 789 uint32_t memory_clock, in tonga_calculate_mclk_params() argument
811 memory_clock, &mpll_param, strobe_mode); in tonga_calculate_mclk_params()
871 freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider); in tonga_calculate_mclk_params()
873 freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider); in tonga_calculate_mclk_params()
906 mclk->MclkFrequency = memory_clock; in tonga_calculate_mclk_params()
920 static uint8_t tonga_get_mclk_frequency_ratio(uint32_t memory_clock, in tonga_get_mclk_frequency_ratio() argument
926 if (memory_clock < 12500) in tonga_get_mclk_frequency_ratio()
928 else if (memory_clock > 47500) in tonga_get_mclk_frequency_ratio()
931 mc_para_index = (uint8_t)((memory_clock - 10000) / 2500); in tonga_get_mclk_frequency_ratio()
933 if (memory_clock < 65000) in tonga_get_mclk_frequency_ratio()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | ppatomctrl.h | 285 …t_memory_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t memory_clock, pp_atomctrl_in…
288 …et_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock);
307 extern int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock,
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| D | smu7_hwmgr.c | 3015 if (smu7_ps->performance_levels[i].memory_clock > max_limits->mclk) in smu7_apply_state_adjust_rules()
3016 smu7_ps->performance_levels[i].memory_clock = max_limits->mclk; in smu7_apply_state_adjust_rules()
3063 mclk = smu7_ps->performance_levels[0].memory_clock; in smu7_apply_state_adjust_rules()
3067 [smu7_ps->performance_level_count - 1].memory_clock; in smu7_apply_state_adjust_rules()
3078 smu7_ps->performance_levels[0].memory_clock = mclk; in smu7_apply_state_adjust_rules()
3087 if (mclk < smu7_ps->performance_levels[1].memory_clock) in smu7_apply_state_adjust_rules()
3088 mclk = smu7_ps->performance_levels[1].memory_clock; in smu7_apply_state_adjust_rules()
3090 smu7_ps->performance_levels[0].memory_clock = mclk; in smu7_apply_state_adjust_rules()
3091 smu7_ps->performance_levels[1].memory_clock = mclk; in smu7_apply_state_adjust_rules()
3093 if (smu7_ps->performance_levels[1].memory_clock < in smu7_apply_state_adjust_rules()
[all …]
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| D | hardwaremanager.c | 397 pclock_info->min_mem_clk = performance_level.memory_clock; in phm_get_clock_info()
407 pclock_info->max_mem_clk = performance_level.memory_clock; in phm_get_clock_info()
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| D | ppatomctrl.c | 175 uint32_t memory_clock) in atomctrl_set_engine_dram_timings_rv770() argument
188 cpu_to_le32(memory_clock & SET_CLOCK_FREQ_MASK); in atomctrl_set_engine_dram_timings_rv770()
1279 const uint32_t memory_clock, in atomctrl_get_memory_clock_spread_spectrum() argument
1283 ASIC_INTERNAL_MEMORY_SS, memory_clock, ssInfo); in atomctrl_get_memory_clock_spread_spectrum()
1318 int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock, in atomctrl_set_ac_timing_ai() argument
1326 memory_clock & SET_CLOCK_FREQ_MASK; in atomctrl_set_ac_timing_ai()
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| D | smu7_hwmgr.h | 55 uint32_t memory_clock; member
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| D | smu10_hwmgr.c | 1022 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk; in smu10_get_performance_level()
1025 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[ in smu10_get_performance_level()
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| D | smu8_hwmgr.c | 1611 level->memory_clock = data->sys_info.nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK - 1]; in smu8_get_performance_level()
1613 level->memory_clock = data->sys_info.nbp_memory_clock[0]; in smu8_get_performance_level()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/inc/ |
| D | hardwaremanager.h | 273 uint32_t memory_clock; member
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| D | amdgpu_smu.h | 193 uint32_t memory_clock; member
324 uint32_t memory_clock; member
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/ |
| D | si_dpm.c | 4269 static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) in si_get_ddr3_mclk_frequency_ratio() argument
4273 if (memory_clock < 10000) in si_get_ddr3_mclk_frequency_ratio()
4275 else if (memory_clock >= 80000) in si_get_ddr3_mclk_frequency_ratio()
4278 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); in si_get_ddr3_mclk_frequency_ratio()
4282 static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) in si_get_mclk_frequency_ratio() argument
4287 if (memory_clock < 12500) in si_get_mclk_frequency_ratio()
4289 else if (memory_clock > 47500) in si_get_mclk_frequency_ratio()
4292 mc_para_index = (u8)((memory_clock - 10000) / 2500); in si_get_mclk_frequency_ratio()
4294 if (memory_clock < 65000) in si_get_mclk_frequency_ratio()
4296 else if (memory_clock > 135000) in si_get_mclk_frequency_ratio()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/swsmu/ |
| D | amdgpu_smu.c | 1388 clk_info->min_mem_clk = level.memory_clock; in smu_get_clock_info()
1396 clk_info->min_mem_clk = level.memory_clock; in smu_get_clock_info()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| D | navi10_ppt.c | 1567 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; in navi10_notify_smc_display_config()
1591 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); in navi10_notify_smc_display_config()
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| D | sienna_cichlid_ppt.c | 1382 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; in sienna_cichlid_notify_smc_display_config()
1406 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); in sienna_cichlid_notify_smc_display_config()
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