Searched refs:pll_28nm (Results 1 – 2 of 2) sorted by relevance
91 static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm, in pll_28nm_poll_for_ready() argument98 val = pll_read(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_STATUS); in pll_28nm_poll_for_ready()111 static void pll_28nm_software_reset(struct dsi_pll_28nm *pll_28nm) in pll_28nm_software_reset() argument113 void __iomem *base = pll_28nm->mmio; in pll_28nm_software_reset()131 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); in dsi_pll_28nm_clk_set_rate() local132 struct device *dev = &pll_28nm->pdev->dev; in dsi_pll_28nm_clk_set_rate()133 void __iomem *base = pll_28nm->mmio; in dsi_pll_28nm_clk_set_rate()224 if (pll_28nm->vco_delay) in dsi_pll_28nm_clk_set_rate()225 udelay(pll_28nm->vco_delay); in dsi_pll_28nm_clk_set_rate()246 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); in dsi_pll_28nm_clk_is_enabled() local[all …]
86 static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm, in pll_28nm_poll_for_ready() argument93 val = pll_read(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_RDY); in pll_28nm_poll_for_ready()113 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); in dsi_pll_28nm_clk_set_rate() local114 void __iomem *base = pll_28nm->mmio; in dsi_pll_28nm_clk_set_rate()154 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); in dsi_pll_28nm_clk_is_enabled() local156 return pll_28nm_poll_for_ready(pll_28nm, POLL_MAX_READS, in dsi_pll_28nm_clk_is_enabled()164 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); in dsi_pll_28nm_clk_recalc_rate() local165 void __iomem *base = pll_28nm->mmio; in dsi_pll_28nm_clk_recalc_rate()289 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); in dsi_pll_28nm_enable_seq() local290 struct device *dev = &pll_28nm->pdev->dev; in dsi_pll_28nm_enable_seq()[all …]