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Searched refs:pll_write (Results 1 – 13 of 13) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/pll/
Ddsi_pll_7nm.c253 pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1, in dsi_pll_ssc_commit()
255 pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1, in dsi_pll_ssc_commit()
257 pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1, in dsi_pll_ssc_commit()
259 pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1, in dsi_pll_ssc_commit()
261 pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1, in dsi_pll_ssc_commit()
263 pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1, in dsi_pll_ssc_commit()
265 pll_write(base + REG_DSI_7nm_PHY_PLL_SSC_CONTROL, in dsi_pll_ssc_commit()
285 pll_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1, in dsi_pll_config_hzindep_reg()
287 pll_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1); in dsi_pll_config_hzindep_reg()
288 pll_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE, 0x01); in dsi_pll_config_hzindep_reg()
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Ddsi_pll_10nm.c252 pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1, in dsi_pll_ssc_commit()
254 pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1, in dsi_pll_ssc_commit()
256 pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1, in dsi_pll_ssc_commit()
258 pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1, in dsi_pll_ssc_commit()
260 pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1, in dsi_pll_ssc_commit()
262 pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1, in dsi_pll_ssc_commit()
264 pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_CONTROL, in dsi_pll_ssc_commit()
273 pll_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE, 0x80); in dsi_pll_config_hzindep_reg()
274 pll_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03); in dsi_pll_config_hzindep_reg()
275 pll_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE, 0x00); in dsi_pll_config_hzindep_reg()
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Ddsi_pll_14nm.c400 pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1, data); in pll_db_commit_ssc()
403 pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2, data); in pll_db_commit_ssc()
407 pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER1, data); in pll_db_commit_ssc()
410 pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER2, data); in pll_db_commit_ssc()
414 pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1, data); in pll_db_commit_ssc()
417 pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2, data); in pll_db_commit_ssc()
422 pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER, data); in pll_db_commit_ssc()
436 pll_write(base + REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET, data); in pll_db_commit_common()
439 pll_write(base + REG_DSI_14nm_PHY_PLL_TXCLK_EN, data); in pll_db_commit_common()
442 pll_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL, data); in pll_db_commit_common()
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Ddsi_pll_28nm.c144 pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG, 3); in dsi_pll_28nm_clk_set_rate()
155 pll_write(base + REG_DSI_28nm_PHY_PLL_LPFR_CFG, lpfr_lut[i].resistance); in dsi_pll_28nm_clk_set_rate()
158 pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70); in dsi_pll_28nm_clk_set_rate()
159 pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15); in dsi_pll_28nm_clk_set_rate()
211 pll_write(base + REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG, 0x02); in dsi_pll_28nm_clk_set_rate()
212 pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG3, 0x2b); in dsi_pll_28nm_clk_set_rate()
213 pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG4, 0x06); in dsi_pll_28nm_clk_set_rate()
214 pll_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); in dsi_pll_28nm_clk_set_rate()
216 pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1, sdm_cfg1); in dsi_pll_28nm_clk_set_rate()
217 pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2, in dsi_pll_28nm_clk_set_rate()
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Ddsi_pll_28nm_8960.c123 pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1, in dsi_pll_28nm_clk_set_rate()
130 pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2, in dsi_pll_28nm_clk_set_rate()
137 pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3, in dsi_pll_28nm_clk_set_rate()
140 pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_6, in dsi_pll_28nm_clk_set_rate()
145 pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, in dsi_pll_28nm_clk_set_rate()
272 pll_write(bytediv->reg, val); in clk_bytediv_set_rate()
313 pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, val); in dsi_pll_28nm_enable_seq()
316 pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, in dsi_pll_28nm_enable_seq()
334 pll_write(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00); in dsi_pll_28nm_disable_seq()
368 pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10, in dsi_pll_28nm_restore_state()
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Ddsi_pll.h42 static inline void pll_write(void __iomem *reg, u32 data) in pll_write() function
54 pll_write(reg, data); in pll_write_udelay()
60 pll_write((reg), data); in pll_write_ndelay()
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/hdmi/
Dhdmi_pll_8960.c237 static inline void pll_write(struct hdmi_pll_8960 *pll, u32 reg, u32 data) in pll_write() function
262 pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x8d); in hdmi_pll_enable()
263 pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0, 0x10); in hdmi_pll_enable()
264 pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1, 0x1a); in hdmi_pll_enable()
274 pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x0d); in hdmi_pll_enable()
301 pll_write(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B, val); in hdmi_pll_enable()
321 pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x8d); in hdmi_pll_enable()
323 pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x0d); in hdmi_pll_enable()
352 pll_write(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B, val); in hdmi_pll_disable()
394 pll_write(pll, pll_rate->conf[i].reg, pll_rate->conf[i].val); in hdmi_pll_set_rate()
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
Datom.h121 void (* pll_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */ member
Dradeon_device.c997 atom_card_info->pll_write = cail_pll_write; in radeon_atombios_init()
Datom.c549 gctx->card->pll_write(gctx->card, idx, val); in atom_put_dst()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
Datom.h123 void (* pll_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */ member
Datom.c545 gctx->card->pll_write(gctx->card, idx, val); in atom_put_dst()
Damdgpu_atombios.c2013 atom_card_info->pll_write = cail_pll_write; in amdgpu_atombios_init()