/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
D | amdgpu_pll.c | 83 static void amdgpu_pll_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, in amdgpu_pll_get_fb_ref_div() argument 88 ref_div_max = min(128 / post_div, ref_div_max); in amdgpu_pll_get_fb_ref_div() 91 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); in amdgpu_pll_get_fb_ref_div() 92 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); in amdgpu_pll_get_fb_ref_div() 126 unsigned post_div_min, post_div_max, post_div; in amdgpu_pll_compute() local 154 post_div_min = pll->post_div; in amdgpu_pll_compute() 155 post_div_max = pll->post_div; in amdgpu_pll_compute() 199 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { in amdgpu_pll_compute() 201 amdgpu_pll_get_fb_ref_div(nom, den, post_div, fb_div_max, in amdgpu_pll_compute() 204 (ref_div * post_div)); in amdgpu_pll_compute() [all …]
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D | atombios_crtc.c | 585 u32 post_div, in amdgpu_atombios_crtc_program_pll() argument 612 args.v1.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll() 622 args.v2.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll() 632 args.v3.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll() 649 args.v5.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll() 679 args.v6.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll() 826 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; in amdgpu_atombios_crtc_set_pll() local 852 pll->post_div = amdgpu_crtc->pll_post_div; in amdgpu_atombios_crtc_set_pll() 855 &fb_div, &frac_fb_div, &ref_div, &post_div); in amdgpu_atombios_crtc_set_pll() 862 ref_div, fb_div, frac_fb_div, post_div, in amdgpu_atombios_crtc_set_pll()
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D | amdgpu_atombios.h | 28 u32 post_div; member 68 u32 post_div; member
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D | atombios_crtc.h | 51 u32 post_div,
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D | si.c | 1560 unsigned post_div = vco_freq / target_freq; in si_uvd_calc_upll_post_div() local 1563 if (post_div < pd_min) in si_uvd_calc_upll_post_div() 1564 post_div = pd_min; in si_uvd_calc_upll_post_div() 1567 if ((vco_freq / post_div) > target_freq) in si_uvd_calc_upll_post_div() 1568 post_div += 1; in si_uvd_calc_upll_post_div() 1571 if (post_div > pd_even && post_div % 2) in si_uvd_calc_upll_post_div() 1572 post_div += 1; in si_uvd_calc_upll_post_div() 1574 return post_div; in si_uvd_calc_upll_post_div()
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D | amdgpu_atombios.c | 1023 dividers->post_div = args.v3.ucPostDiv; in amdgpu_atombios_get_clock_dividers() 1043 dividers->post_div = args.v5.ucPostDiv; in amdgpu_atombios_get_clock_dividers() 1061 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; in amdgpu_atombios_get_clock_dividers() 1075 dividers->post_div = args.v6_out.ucPllPostDiv; in amdgpu_atombios_get_clock_dividers() 1115 mpll_param->post_div = args.ucPostDiv; in amdgpu_atombios_get_memory_pll_dividers()
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D | amdgpu_mode.h | 197 uint32_t post_div; member
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/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
D | radeon_clocks.c | 43 uint32_t fb_div, ref_div, post_div, sclk; in radeon_legacy_get_engine_clock() local 58 post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK; in radeon_legacy_get_engine_clock() 59 if (post_div == 2) in radeon_legacy_get_engine_clock() 61 else if (post_div == 3) in radeon_legacy_get_engine_clock() 63 else if (post_div == 4) in radeon_legacy_get_engine_clock() 73 uint32_t fb_div, ref_div, post_div, mclk; in radeon_legacy_get_memory_clock() local 88 post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7; in radeon_legacy_get_memory_clock() 89 if (post_div == 2) in radeon_legacy_get_memory_clock() 91 else if (post_div == 3) in radeon_legacy_get_memory_clock() 93 else if (post_div == 4) in radeon_legacy_get_memory_clock() [all …]
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D | radeon_display.c | 932 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, in avivo_get_fb_ref_div() argument 937 ref_div_max = max(min(100 / post_div, ref_div_max), 1u); in avivo_get_fb_ref_div() 940 *ref_div = min(max(den/post_div, 1u), ref_div_max); in avivo_get_fb_ref_div() 941 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); in avivo_get_fb_ref_div() 975 unsigned post_div_min, post_div_max, post_div; in radeon_compute_pll_avivo() local 1006 post_div_min = pll->post_div; in radeon_compute_pll_avivo() 1007 post_div_max = pll->post_div; in radeon_compute_pll_avivo() 1051 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { in radeon_compute_pll_avivo() 1053 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, in radeon_compute_pll_avivo() 1056 (ref_div * post_div)); in radeon_compute_pll_avivo() [all …]
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D | radeon_legacy_tv.c | 856 int post_div; in get_post_div() local 858 case 1: post_div = 0; break; in get_post_div() 859 case 2: post_div = 1; break; in get_post_div() 860 case 3: post_div = 4; break; in get_post_div() 861 case 4: post_div = 2; break; in get_post_div() 862 case 6: post_div = 6; break; in get_post_div() 863 case 8: post_div = 3; break; in get_post_div() 864 case 12: post_div = 7; break; in get_post_div() 866 default: post_div = 5; break; in get_post_div() 868 return post_div; in get_post_div()
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D | rv730_dpm.c | 64 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_sclk_value() 65 (dividers.post_div & 0xf) + 2; in rv730_populate_sclk_value() 80 spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf); in rv730_populate_sclk_value() 81 spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf); in rv730_populate_sclk_value() 142 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_mclk_value() 143 (dividers.post_div & 0xf) + 2; in rv730_populate_mclk_value() 155 mpll_func_cntl |= MPLL_HILEN((dividers.post_div >> 4) & 0xf); in rv730_populate_mclk_value() 156 mpll_func_cntl |= MPLL_LOLEN(dividers.post_div & 0xf); in rv730_populate_mclk_value()
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D | rv740_dpm.c | 143 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in rv740_populate_sclk_value() 149 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); in rv740_populate_sclk_value() 160 u32 vco_freq = engine_clock * dividers.post_div; in rv740_populate_sclk_value() 217 mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div); in rv740_populate_mclk_value() 234 mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div); in rv740_populate_mclk_value() 247 u32 vco_freq = memory_clock * dividers.post_div; in rv740_populate_mclk_value()
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D | radeon_uvd.c | 922 unsigned post_div = vco_freq / target_freq; in radeon_uvd_calc_upll_post_div() local 925 if (post_div < pd_min) in radeon_uvd_calc_upll_post_div() 926 post_div = pd_min; in radeon_uvd_calc_upll_post_div() 929 if ((vco_freq / post_div) > target_freq) in radeon_uvd_calc_upll_post_div() 930 post_div += 1; in radeon_uvd_calc_upll_post_div() 933 if (post_div > pd_even && post_div % 2) in radeon_uvd_calc_upll_post_div() 934 post_div += 1; in radeon_uvd_calc_upll_post_div() 936 return post_div; in radeon_uvd_calc_upll_post_div()
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D | radeon_legacy_crtc.c | 756 } *post_div, post_divs[] = { in radeon_set_pll() local 822 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { in radeon_set_pll() 823 if (post_div->divider == post_divider) in radeon_set_pll() 827 if (!post_div->divider) in radeon_set_pll() 828 post_div = &post_divs[0]; in radeon_set_pll() 843 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16)); in radeon_set_pll()
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D | rs780_dpm.c | 89 r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div); in rs780_initialize_dpm_power_state() 455 (min_dividers.post_div != max_dividers.post_div) || in rs780_set_engine_clock_scaling() 457 (max_dividers.post_div != current_max_dividers.post_div)) in rs780_set_engine_clock_scaling() 990 u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 + in rs780_dpm_debugfs_print_current_performance_level() local 993 (post_div * ref_div); in rs780_dpm_debugfs_print_current_performance_level() 1012 u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 + in rs780_dpm_get_current_sclk() local 1015 (post_div * ref_div); in rs780_dpm_get_current_sclk()
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D | atombios_crtc.c | 831 u32 post_div, in atombios_crtc_program_pll() argument 858 args.v1.ucPostDiv = post_div; in atombios_crtc_program_pll() 868 args.v2.ucPostDiv = post_div; in atombios_crtc_program_pll() 878 args.v3.ucPostDiv = post_div; in atombios_crtc_program_pll() 895 args.v5.ucPostDiv = post_div; in atombios_crtc_program_pll() 924 args.v6.ucPostDiv = post_div; in atombios_crtc_program_pll() 1071 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; in atombios_crtc_set_pll() local 1098 pll->post_div = radeon_crtc->pll_post_div; in atombios_crtc_set_pll() 1103 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll() 1106 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll() [all …]
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D | radeon_mode.h | 171 uint32_t post_div; member 579 u32 post_div; member 619 u32 post_div; member
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D | rv770_dpm.c | 332 post_divider = dividers->post_div; in rv770_calculate_fractional_mpll_feedback_divider() 421 ret = rv770_encode_yclk_post_div(dividers.post_div, &postdiv_yclk); in rv770_populate_mclk_value() 451 ret = rv770_encode_yclk_post_div(dividers.post_div, &postdiv_yclk); in rv770_populate_mclk_value() 513 post_divider = (0x0f & (dividers.post_div >> 4)) + (0x0f & dividers.post_div) + 2; in rv770_populate_sclk_value() 527 spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf); in rv770_populate_sclk_value() 528 spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf); in rv770_populate_sclk_value()
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D | kv_dpm.c | 546 pi->graphics_level[index].SclkDid = (u8)dividers.post_div; in kv_set_divider_value() 849 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table() 855 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table() 917 pi->vce_level[i].Divider = (u8)dividers.post_div; in kv_populate_vce_table() 980 pi->samu_level[i].Divider = (u8)dividers.post_div; in kv_populate_samu_table() 1039 pi->acp_level[i].Divider = (u8)dividers.post_div; in kv_populate_acp_table()
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/kernel/linux/linux-5.10/drivers/clk/ |
D | clk-stm32f4.c | 1760 const struct stm32f4_pll_post_div_data *post_div; in stm32f4_rcc_init() local 1763 post_div = &post_div_data[n]; in stm32f4_rcc_init() 1765 hw = clk_register_pll_div(post_div->name, in stm32f4_rcc_init() 1766 post_div->parent, in stm32f4_rcc_init() 1767 post_div->flag, in stm32f4_rcc_init() 1768 base + post_div->offset, in stm32f4_rcc_init() 1769 post_div->shift, in stm32f4_rcc_init() 1770 post_div->width, in stm32f4_rcc_init() 1771 post_div->flag_div, in stm32f4_rcc_init() 1772 post_div->div_table, in stm32f4_rcc_init() [all …]
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/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
D | mcp77.c | 55 u32 post_div = 0; in read_pll() local 61 post_div = 1 << ((nvkm_rd32(device, 0x4070) & 0x000f0000) >> 16); in read_pll() 64 post_div = (nvkm_rd32(device, 0x4040) & 0x000f0000) >> 16; in read_pll() 74 clock = clock / post_div; in read_pll()
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/kernel/linux/linux-5.10/drivers/video/fbdev/aty/ |
D | radeon_base.c | 1526 } *post_div, in radeon_calc_pll_regs() local 1595 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { in radeon_calc_pll_regs() 1596 pll_output_freq = post_div->divider * freq; in radeon_calc_pll_regs() 1600 if (uses_dvo && (post_div->divider & 1)) in radeon_calc_pll_regs() 1609 if ( !post_div->divider ) { in radeon_calc_pll_regs() 1610 post_div = &post_divs[post_div->bitvalue]; in radeon_calc_pll_regs() 1611 pll_output_freq = post_div->divider * freq; in radeon_calc_pll_regs() 1619 if ( !post_div->divider ) { in radeon_calc_pll_regs() 1620 post_div = &post_divs[post_div->bitvalue]; in radeon_calc_pll_regs() 1621 pll_output_freq = post_div->divider * freq; in radeon_calc_pll_regs() [all …]
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D | radeonfb.h | 233 int post_div; member
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/kernel/linux/linux-5.10/drivers/media/tuners/ |
D | tda18271-priv.h | 180 u32 *freq, u8 *post_div, u8 *div);
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D | tda18271-maps.c | 1053 u32 *freq, u8 *post_div, u8 *div) in tda18271_lookup_pll_map() argument 1093 *post_div = map[i].pd; in tda18271_lookup_pll_map() 1097 i, map_name, *post_div, *div); in tda18271_lookup_pll_map()
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