/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
D | ni_dma.c | 159 u32 rb_cntl; in cayman_dma_stop() local 166 rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in cayman_dma_stop() 167 rb_cntl &= ~DMA_RB_ENABLE; in cayman_dma_stop() 168 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop() 171 rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in cayman_dma_stop() 172 rb_cntl &= ~DMA_RB_ENABLE; in cayman_dma_stop() 173 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop() 190 u32 rb_cntl, dma_cntl, ib_cntl; in cayman_dma_resume() local 211 rb_cntl = rb_bufsz << 1; in cayman_dma_resume() 213 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; in cayman_dma_resume() [all …]
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D | r600_dma.c | 101 u32 rb_cntl = RREG32(DMA_RB_CNTL); in r600_dma_stop() local 106 rb_cntl &= ~DMA_RB_ENABLE; in r600_dma_stop() 107 WREG32(DMA_RB_CNTL, rb_cntl); in r600_dma_stop() 123 u32 rb_cntl, dma_cntl, ib_cntl; in r600_dma_resume() local 132 rb_cntl = rb_bufsz << 1; in r600_dma_resume() 134 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; in r600_dma_resume() 136 WREG32(DMA_RB_CNTL, rb_cntl); in r600_dma_resume() 149 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; in r600_dma_resume() 170 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE); in r600_dma_resume()
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D | cik_sdma.c | 252 u32 rb_cntl, reg_offset; in cik_sdma_gfx_stop() local 264 rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset); in cik_sdma_gfx_stop() 265 rb_cntl &= ~SDMA_RB_ENABLE; in cik_sdma_gfx_stop() 266 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); in cik_sdma_gfx_stop() 368 u32 rb_cntl, ib_cntl; in cik_sdma_gfx_resume() local 389 rb_cntl = rb_bufsz << 1; in cik_sdma_gfx_resume() 391 rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE; in cik_sdma_gfx_resume() 393 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); in cik_sdma_gfx_resume() 406 rb_cntl |= SDMA_RPTR_WRITEBACK_ENABLE; in cik_sdma_gfx_resume() 415 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE); in cik_sdma_gfx_resume()
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D | ni.c | 1689 uint32_t rb_cntl; in cayman_cp_resume() local 1694 rb_cntl = order_base_2(ring->ring_size / 8); in cayman_cp_resume() 1695 rb_cntl |= order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8; in cayman_cp_resume() 1697 rb_cntl |= BUF_SWAP_32BIT; in cayman_cp_resume() 1699 WREG32(cp_rb_cntl[i], rb_cntl); in cayman_cp_resume()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
D | sdma_v2_4.c | 343 u32 rb_cntl, ib_cntl; in sdma_v2_4_gfx_stop() local 351 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in sdma_v2_4_gfx_stop() 352 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v2_4_gfx_stop() 353 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in sdma_v2_4_gfx_stop() 411 u32 rb_cntl, ib_cntl; in sdma_v2_4_gfx_resume() local 437 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in sdma_v2_4_gfx_resume() 438 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v2_4_gfx_resume() 440 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); in sdma_v2_4_gfx_resume() 441 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, in sdma_v2_4_gfx_resume() 444 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in sdma_v2_4_gfx_resume() [all …]
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D | sdma_v4_0.c | 960 u32 rb_cntl, ib_cntl; in sdma_v4_0_gfx_stop() local 971 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); in sdma_v4_0_gfx_stop() 972 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v4_0_gfx_stop() 973 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); in sdma_v4_0_gfx_stop() 1002 u32 rb_cntl, ib_cntl; in sdma_v4_0_page_stop() local 1015 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); in sdma_v4_0_page_stop() 1016 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, in sdma_v4_0_page_stop() 1018 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); in sdma_v4_0_page_stop() 1116 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) in sdma_v4_0_rb_cntl() argument 1121 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v4_0_rb_cntl() [all …]
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D | sdma_v3_0.c | 517 u32 rb_cntl, ib_cntl; in sdma_v3_0_gfx_stop() local 525 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in sdma_v3_0_gfx_stop() 526 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v3_0_gfx_stop() 527 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in sdma_v3_0_gfx_stop() 646 u32 rb_cntl, ib_cntl, wptr_poll_cntl; in sdma_v3_0_gfx_resume() local 675 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in sdma_v3_0_gfx_resume() 676 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v3_0_gfx_resume() 678 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); in sdma_v3_0_gfx_resume() 679 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, in sdma_v3_0_gfx_resume() 682 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in sdma_v3_0_gfx_resume() [all …]
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D | sdma_v5_2.c | 462 u32 rb_cntl, ib_cntl; in sdma_v5_2_gfx_stop() local 472 rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_2_gfx_stop() 473 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v5_2_gfx_stop() 474 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); in sdma_v5_2_gfx_stop() 583 u32 rb_cntl, ib_cntl; in sdma_v5_2_gfx_resume() local 601 rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_2_gfx_resume() 602 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v5_2_gfx_resume() 604 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); in sdma_v5_2_gfx_resume() 605 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, in sdma_v5_2_gfx_resume() 608 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); in sdma_v5_2_gfx_resume() [all …]
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D | si_dma.c | 115 u32 rb_cntl; in si_dma_stop() local 121 rb_cntl = RREG32(DMA_RB_CNTL + sdma_offsets[i]); in si_dma_stop() 122 rb_cntl &= ~DMA_RB_ENABLE; in si_dma_stop() 123 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); in si_dma_stop() 133 u32 rb_cntl, dma_cntl, ib_cntl, rb_bufsz; in si_dma_start() local 145 rb_cntl = rb_bufsz << 1; in si_dma_start() 147 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; in si_dma_start() 149 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); in si_dma_start() 160 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; in si_dma_start() 177 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl | DMA_RB_ENABLE); in si_dma_start()
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D | sdma_v5_0.c | 526 u32 rb_cntl, ib_cntl; in sdma_v5_0_gfx_stop() local 534 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_0_gfx_stop() 535 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v5_0_gfx_stop() 536 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); in sdma_v5_0_gfx_stop() 652 u32 rb_cntl, ib_cntl; in sdma_v5_0_gfx_resume() local 671 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_0_gfx_resume() 672 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v5_0_gfx_resume() 674 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); in sdma_v5_0_gfx_resume() 675 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, in sdma_v5_0_gfx_resume() 678 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); in sdma_v5_0_gfx_resume() [all …]
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D | cik_sdma.c | 310 u32 rb_cntl; in cik_sdma_gfx_stop() local 318 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in cik_sdma_gfx_stop() 319 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK; in cik_sdma_gfx_stop() 320 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in cik_sdma_gfx_stop() 433 u32 rb_cntl, ib_cntl; in cik_sdma_gfx_resume() local 461 rb_cntl = rb_bufsz << 1; in cik_sdma_gfx_resume() 463 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK | in cik_sdma_gfx_resume() 466 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in cik_sdma_gfx_resume() 480 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK; in cik_sdma_gfx_resume() 490 rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK); in cik_sdma_gfx_resume()
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