Searched refs:reg_val_offs (Results 1 – 6 of 6) sorted by relevance
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_gfx.c | 710 uint32_t seq, reg_val_offs = 0, value = 0; in amdgpu_kiq_rreg() local
720 if (amdgpu_device_wb_get(adev, ®_val_offs)) { in amdgpu_kiq_rreg()
725 amdgpu_ring_emit_rreg(ring, reg, reg_val_offs); in amdgpu_kiq_rreg()
756 value = adev->wb.wb[reg_val_offs]; in amdgpu_kiq_rreg()
757 amdgpu_device_wb_free(adev, reg_val_offs); in amdgpu_kiq_rreg()
765 if (reg_val_offs) in amdgpu_kiq_rreg()
766 amdgpu_device_wb_free(adev, reg_val_offs); in amdgpu_kiq_rreg()
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| D | amdgpu_virt.h | 206 uint32_t reg_val_offs; member
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| D | amdgpu_ring.h | 187 uint32_t reg_val_offs);
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| D | gfx_v9_0.c | 4083 uint32_t seq, reg_val_offs = 0; in gfx_v9_0_kiq_read_clock() local
4091 if (amdgpu_device_wb_get(adev, ®_val_offs)) { in gfx_v9_0_kiq_read_clock()
4104 reg_val_offs * 4)); in gfx_v9_0_kiq_read_clock()
4106 reg_val_offs * 4)); in gfx_v9_0_kiq_read_clock()
4137 value = (uint64_t)adev->wb.wb[reg_val_offs] | in gfx_v9_0_kiq_read_clock()
4138 (uint64_t)adev->wb.wb[reg_val_offs + 1 ] << 32ULL; in gfx_v9_0_kiq_read_clock()
4139 amdgpu_device_wb_free(adev, reg_val_offs); in gfx_v9_0_kiq_read_clock()
4147 if (reg_val_offs) in gfx_v9_0_kiq_read_clock()
4148 amdgpu_device_wb_free(adev, reg_val_offs); in gfx_v9_0_kiq_read_clock()
5564 uint32_t reg_val_offs) in gfx_v9_0_ring_emit_rreg() argument
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| D | gfx_v8_0.c | 6386 uint32_t reg_val_offs) in gfx_v8_0_ring_emit_rreg() argument
6397 reg_val_offs * 4)); in gfx_v8_0_ring_emit_rreg()
6399 reg_val_offs * 4)); in gfx_v8_0_ring_emit_rreg()
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| D | gfx_v10_0.c | 8130 uint32_t reg_val_offs) in gfx_v10_0_ring_emit_rreg() argument
8141 reg_val_offs * 4)); in gfx_v10_0_ring_emit_rreg()
8143 reg_val_offs * 4)); in gfx_v10_0_ring_emit_rreg()
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