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Searched refs:tWHR_min (Results 1 – 10 of 10) sorted by relevance

/kernel/linux/linux-5.10/drivers/mtd/nand/raw/
Dnand_timings.c63 .tWHR_min = 120000,
108 .tWHR_min = 80000,
153 .tWHR_min = 80000,
198 .tWHR_min = 80000,
243 .tWHR_min = 80000,
288 .tWHR_min = 80000,
339 spec_timings->tWHR_min <= onfi_timings->tWHR_min && in onfi_find_closest_sdr_mode()
Dnand_toshiba.c237 sdr->tWHR_min = 60000; in th58nvg2s3hbai4_choose_interface_config()
Dstm32_fmc2_nand.c1506 if (sdrt->tWHR_min > tset_mem && in stm32_fmc2_nfc_calc_timings()
1507 (thold_att < sdrt->tWHR_min - tset_mem)) in stm32_fmc2_nfc_calc_timings()
1508 thold_att = sdrt->tWHR_min - tset_mem; in stm32_fmc2_nfc_calc_timings()
Dsunxi_nand.c1460 if (timings->tWHR_min > (min_clk_period * 32)) in sunxi_nfc_setup_interface()
1461 min_clk_period = DIV_ROUND_UP(timings->tWHR_min, 32); in sunxi_nfc_setup_interface()
1493 tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3; in sunxi_nfc_setup_interface()
Dtegra_nand.c803 reg |= TIMING_TWHR(OFFSET(DIV_ROUND_UP(timings->tWHR_min, period), 1)); in tegra_nand_setup_timing()
Ddenali.c824 we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), t_x); in denali_setup_interface()
Dmtk_nand.c567 tw2r = timings->tWHR_min / 1000; in mtk_nfc_setup_interface()
Dmarvell_nand.c2398 nfc_tmg.tWHR = TO_CYCLES(max_t(int, sdr->tWHR_min, sdr->tCCS_min), in marvell_nfc_setup_interface()
Dcadence-nand-controller.c2473 twhr_cnt = calc_cycl((sdr->tWHR_min + if_skew), clk_period); in cadence_nand_setup_interface()
/kernel/linux/linux-5.10/include/linux/mtd/
Drawnand.h472 u32 tWHR_min; member