tc_port (reference) in projects: kernel

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Searched refs:tc_port (Results 1 – 8 of 8) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
D	intel_dpll_mgr.c	3093 static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id) in icl_pll_id_to_tc_port() 3098 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port) in icl_tc_port_to_pll_id() argument 3100 return tc_port + DPLL_ID_ICL_MGPLL1; in icl_tc_port_to_pll_id() 3680 enum tc_port tc_port = icl_pll_id_to_tc_port(id); in mg_pll_get_hw_state() local 3690 val = intel_de_read(dev_priv, MG_PLL_ENABLE(tc_port)); in mg_pll_get_hw_state() 3695 MG_REFCLKIN_CTL(tc_port)); in mg_pll_get_hw_state() 3699 intel_de_read(dev_priv, MG_CLKTOP2_CORECLKCTL1(tc_port)); in mg_pll_get_hw_state() 3704 intel_de_read(dev_priv, MG_CLKTOP2_HSCLKCTL(tc_port)); in mg_pll_get_hw_state() 3711 hw_state->mg_pll_div0 = intel_de_read(dev_priv, MG_PLL_DIV0(tc_port)); in mg_pll_get_hw_state() 3712 hw_state->mg_pll_div1 = intel_de_read(dev_priv, MG_PLL_DIV1(tc_port)); in mg_pll_get_hw_state() [all …]
D	intel_tc.c	641 enum tc_port tc_port = intel_port_to_tc(i915, port); in tc_port_load_fia_params() local 648 dig_port->tc_phy_fia = tc_port / 2; in tc_port_load_fia_params() 649 dig_port->tc_phy_fia_idx = tc_port % 2; in tc_port_load_fia_params() 652 dig_port->tc_phy_fia_idx = tc_port; in tc_port_load_fia_params() 660 enum tc_port tc_port = intel_port_to_tc(i915, port); in intel_tc_port_init() local 662 if (drm_WARN_ON(&i915->drm, tc_port == PORT_TC_NONE)) in intel_tc_port_init() 666 "%c/TC#%d", port_name(port), tc_port + 1); in intel_tc_port_init()
D	intel_ddi.c	2595 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); in icl_mg_phy_ddi_vswing_sequence() local 2620 val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port)); in icl_mg_phy_ddi_vswing_sequence() 2622 intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val); in icl_mg_phy_ddi_vswing_sequence() 2624 val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port)); in icl_mg_phy_ddi_vswing_sequence() 2626 intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val); in icl_mg_phy_ddi_vswing_sequence() 2631 val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port)); in icl_mg_phy_ddi_vswing_sequence() 2635 intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val); in icl_mg_phy_ddi_vswing_sequence() 2637 val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port)); in icl_mg_phy_ddi_vswing_sequence() 2641 intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val); in icl_mg_phy_ddi_vswing_sequence() 2646 val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port)); in icl_mg_phy_ddi_vswing_sequence() [all …]
D	intel_dpll_mgr.h	`396 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);`
D	intel_display.h	`245 enum tc_port { enum 535 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,`
D	intel_display_power.c	`630 enum tc_port tc_port; in icl_tc_phy_aux_power_well_enable() local 632 tc_port = TGL_AUX_PW_TO_TC_PORT(power_well->desc->hsw.idx); in icl_tc_phy_aux_power_well_enable() 633 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), in icl_tc_phy_aux_power_well_enable() 634 HIP_INDEX_VAL(tc_port, 0x2)); in icl_tc_phy_aux_power_well_enable() 636 if (intel_de_wait_for_set(dev_priv, DKL_CMN_UC_DW_27(tc_port), in icl_tc_phy_aux_power_well_enable()`
D	intel_display.c	`7307 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) in intel_port_to_tc()`
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
D	i915_reg.h	2091 #define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \ argument 2092 _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1))) 2102 #define MG_TX1_LINK_PARAMS(ln, tc_port) \ argument 2103 MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \ 2115 #define MG_TX2_LINK_PARAMS(ln, tc_port) \ argument 2116 MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \ 2129 #define MG_TX1_PISO_READLOAD(ln, tc_port) \ argument 2130 MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \ 2142 #define MG_TX2_PISO_READLOAD(ln, tc_port) \ argument 2143 MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \ [all …]