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Searched refs:training_lane (Results 1 – 4 of 4) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/bridge/analogix/
Danalogix_dp_core.h152 u8 training_lane[4]; member
225 u32 training_lane);
227 u32 training_lane);
229 u32 training_lane);
231 u32 training_lane);
Danalogix_dp_core.c446 u8 voltage_swing, pre_emphasis, training_lane; in analogix_dp_get_adjust_training_lane() local
454 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | in analogix_dp_get_adjust_training_lane()
458 training_lane |= DP_TRAIN_MAX_SWING_REACHED; in analogix_dp_get_adjust_training_lane()
460 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; in analogix_dp_get_adjust_training_lane()
462 dp->link_train.training_lane[lane] = training_lane; in analogix_dp_get_adjust_training_lane()
469 u8 voltage_swing, pre_emphasis, training_lane; in analogix_dp_process_clock_recovery() local
499 training_lane = analogix_dp_get_lane_link_training( in analogix_dp_process_clock_recovery()
506 if (DPCD_VOLTAGE_SWING_GET(training_lane) == in analogix_dp_process_clock_recovery()
508 DPCD_PRE_EMPHASIS_GET(training_lane) == in analogix_dp_process_clock_recovery()
528 dp->link_train.training_lane[lane], lane); in analogix_dp_process_clock_recovery()
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Danalogix_dp_reg.c742 u32 training_lane) in analogix_dp_set_lane0_link_training() argument
746 reg = training_lane; in analogix_dp_set_lane0_link_training()
751 u32 training_lane) in analogix_dp_set_lane1_link_training() argument
755 reg = training_lane; in analogix_dp_set_lane1_link_training()
760 u32 training_lane) in analogix_dp_set_lane2_link_training() argument
764 reg = training_lane; in analogix_dp_set_lane2_link_training()
769 u32 training_lane) in analogix_dp_set_lane3_link_training() argument
773 reg = training_lane; in analogix_dp_set_lane3_link_training()
/kernel/linux/patches/linux-5.10/yangfan_patch/
Ddrivers.patch7779 + dp->link_train.training_lane[lane] =
7861 u8 voltage_swing, pre_emphasis, training_lane;
7897 - dp->link_train.training_lane[lane], lane);
7901 dp->link_train.training_lane, lane_count);
7922 - dp->link_train.training_lane[lane], lane);
7926 dp->link_train.training_lane, lane_count);
8020 - dp->link_train.training_lane[i], i);
8861 + dp->link_train.training_lane[lane] =
9152 u8 training_lane[4];
9217 - u32 training_lane);
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