Searched refs:triggered_crtc_reset (Results 1 – 5 of 5) sorted by relevance
205 struct crtc_trigger_info triggered_crtc_reset; member
4653 if (stream->triggered_crtc_reset.enabled) { in set_multisync_trigger_params()4654 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING; in set_multisync_trigger_params()4655 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE; in set_multisync_trigger_params()4665 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { in set_master_stream()4678 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; in set_master_stream()8180 new_stream->triggered_crtc_reset.enabled = in dm_update_crtc_state()9296 ->triggered_crtc_reset.enabled = in amdgpu_dm_trigger_timing_sync()
1024 !ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled) in enable_timing_multisync()1026 …if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event… in enable_timing_multisync()
2416 &grouped_pipes[i]->stream->triggered_crtc_reset); in dce110_enable_per_frame_crtc_position_reset()
1901 &grouped_pipes[i]->stream->triggered_crtc_reset); in dcn10_enable_per_frame_crtc_position_reset()