| /kernel/linux/linux-5.10/arch/arm64/include/asm/ |
| D | mmu_context.h | 43 unsigned long ttbr = phys_to_ttbr(__pa_symbol(reserved_pg_dir)); in cpu_set_reserved_ttbr0() local
45 write_sysreg(ttbr, ttbr0_el1); in cpu_set_reserved_ttbr0()
189 u64 ttbr; in update_saved_ttbr0() local
195 ttbr = phys_to_ttbr(__pa_symbol(reserved_pg_dir)); in update_saved_ttbr0()
197 ttbr = phys_to_ttbr(virt_to_phys(mm->pgd)) | ASID(mm) << 48; in update_saved_ttbr0()
199 WRITE_ONCE(task_thread_info(tsk)->ttbr0, ttbr); in update_saved_ttbr0()
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| D | assembler.h | 542 .macro offset_ttbr1, ttbr, tmp
547 orr \ttbr, \ttbr, #TTBR1_BADDR_4852_OFFSET
557 .macro restore_ttbr1, ttbr
559 bic \ttbr, \ttbr, #TTBR1_BADDR_4852_OFFSET
570 .macro phys_to_ttbr, ttbr, phys
572 orr \ttbr, \phys, \phys, lsr #46
573 and \ttbr, \ttbr, #TTBR_BADDR_MASK_52
575 mov \ttbr, \phys
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| D | uaccess.h | 111 unsigned long flags, ttbr; in __uaccess_ttbr0_disable() local
114 ttbr = read_sysreg(ttbr1_el1); in __uaccess_ttbr0_disable()
115 ttbr &= ~TTBR_ASID_MASK; in __uaccess_ttbr0_disable()
117 write_sysreg(ttbr - PAGE_SIZE, ttbr0_el1); in __uaccess_ttbr0_disable()
120 write_sysreg(ttbr, ttbr1_el1); in __uaccess_ttbr0_disable()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/ |
| D | msm_iommu.c | 24 phys_addr_t ttbr; member
101 phys_addr_t *ttbr, int *asid) in msm_iommu_pagetable_params() argument
110 if (ttbr) in msm_iommu_pagetable_params()
111 *ttbr = pagetable->ttbr; in msm_iommu_pagetable_params()
198 pagetable->ttbr = ttbr0_cfg.arm_lpae_s1_cfg.ttbr; in msm_iommu_pagetable_create()
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| D | msm_mmu.h | 58 int msm_iommu_pagetable_params(struct msm_mmu *mmu, phys_addr_t *ttbr,
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| /kernel/linux/linux-5.10/arch/arm/include/asm/ |
| D | proc-fns.h | 160 u64 ttbr; \
162 : "=r" (ttbr)); \
163 ttbr; \
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| /kernel/linux/linux-5.10/include/linux/ |
| D | io-pgtable.h | 107 u64 ttbr; member
133 u32 ttbr; member
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| /kernel/linux/linux-5.10/drivers/iommu/arm/arm-smmu/ |
| D | arm-smmu.c | 508 cb->ttbr[0] = pgtbl_cfg->arm_v7s_cfg.ttbr; in arm_smmu_init_context_bank()
509 cb->ttbr[1] = 0; in arm_smmu_init_context_bank()
511 cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, in arm_smmu_init_context_bank()
513 cb->ttbr[1] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, in arm_smmu_init_context_bank()
517 cb->ttbr[1] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr; in arm_smmu_init_context_bank()
519 cb->ttbr[0] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr; in arm_smmu_init_context_bank()
522 cb->ttbr[0] = pgtbl_cfg->arm_lpae_s2_cfg.vttbr; in arm_smmu_init_context_bank()
597 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TTBR0, cb->ttbr[0]); in arm_smmu_write_context_bank()
598 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TTBR1, cb->ttbr[1]); in arm_smmu_write_context_bank()
600 arm_smmu_cb_writeq(smmu, idx, ARM_SMMU_CB_TTBR0, cb->ttbr[0]); in arm_smmu_write_context_bank()
[all …]
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| D | arm-smmu.h | 350 u64 ttbr[2]; member
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| D | qcom_iommu.c | 288 pgtbl_cfg.arm_lpae_s1_cfg.ttbr | in qcom_iommu_init_domain()
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| /kernel/linux/linux-5.10/drivers/iommu/ |
| D | ipmmu-vmsa.c | 370 u64 ttbr; in ipmmu_domain_setup_context() local
374 ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr; in ipmmu_domain_setup_context()
375 ipmmu_ctx_write_root(domain, IMTTLBR0, ttbr); in ipmmu_domain_setup_context()
376 ipmmu_ctx_write_root(domain, IMTTUBR0, ttbr >> 32); in ipmmu_domain_setup_context()
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| D | mtk_iommu.c | 397 writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, in mtk_iommu_attach_device()
820 writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, in mtk_iommu_resume()
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| D | msm_iommu.c | 282 SET_TTBR0(base, ctx, priv->cfg.arm_v7s_cfg.ttbr); in __program_context()
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| D | io-pgtable-arm-v7s.c | 828 cfg->arm_v7s_cfg.ttbr = virt_to_phys(data->pgd) | ARM_V7S_TTBR_S | in arm_v7s_alloc_pgtable()
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| D | io-pgtable-arm.c | 852 cfg->arm_lpae_s1_cfg.ttbr = virt_to_phys(data->pgd); in arm_64_lpae_alloc_pgtable_s1()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/adreno/ |
| D | a6xx_gpu.c | 98 phys_addr_t ttbr; in a6xx_set_pagetable() local
105 if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid)) in a6xx_set_pagetable()
110 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr))); in a6xx_set_pagetable()
113 CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) | in a6xx_set_pagetable()
124 OUT_RING(ring, lower_32_bits(ttbr)); in a6xx_set_pagetable()
125 OUT_RING(ring, (asid << 16) | upper_32_bits(ttbr)); in a6xx_set_pagetable()
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| /kernel/liteos_a/arch/arm/arm/src/ |
| D | los_arch_mmu.c | 927 UINT32 ttbr; in LOS_ArchMmuContextSwitch() local
930 ttbr = MMU_TTBRx_FLAGS | (archMmu->physTtb); in LOS_ArchMmuContextSwitch()
934 ttbr = 0; in LOS_ArchMmuContextSwitch()
944 OsArmWriteTtbr0(ttbr); in LOS_ArchMmuContextSwitch()
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| /kernel/linux/linux-5.10/drivers/iommu/arm/arm-smmu-v3/ |
| D | arm-smmu-v3-sva.c | 127 cd->ttbr = virt_to_phys(mm->pgd); in arm_smmu_alloc_shared_cd()
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| D | arm-smmu-v3.h | 540 u64 ttbr; member
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| D | arm-smmu-v3.c | 1013 cdptr[1] = cpu_to_le64(cd->ttbr & CTXDESC_CD_1_TTB0_MASK); in arm_smmu_write_ctx_desc()
1872 cfg->cd.ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; in arm_smmu_domain_finalise_s1()
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| /kernel/linux/patches/linux-5.10/hispark_taurus_patch/ |
| D | hispark_taurus.patch | 19852 + /* set ttbr */
19856 + /* only [31:10] is the ttbr */
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| /kernel/linux/patches/linux-4.19/hispark_taurus_patch/ |
| D | hispark_taurus.patch | 302894 + /* set ttbr */
302898 + /* only [31:10] is the ttbr */
|