| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/ |
| D | intel_uncore.c | 107 GEM_BUG_ON(d->uncore->fw_domains_timer & d->mask); in fw_domain_arm_timer()
108 d->uncore->fw_domains_timer |= d->mask; in fw_domain_arm_timer()
145 add_taint_for_CI(d->uncore->i915, TAINT_WARN); /* CI now unreliable */ in fw_domain_wait_ack_clear()
222 add_taint_for_CI(d->uncore->i915, TAINT_WARN); /* CI now unreliable */ in fw_domain_wait_ack_set()
243 fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains) in fw_domains_get() argument
248 GEM_BUG_ON(fw_domains & ~uncore->fw_domains); in fw_domains_get()
250 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) { in fw_domains_get()
255 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) in fw_domains_get()
258 uncore->fw_domains_active |= fw_domains; in fw_domains_get()
262 fw_domains_get_with_fallback(struct intel_uncore *uncore, in fw_domains_get_with_fallback() argument
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| D | vlv_suspend.c | 108 struct intel_uncore *uncore = &i915->uncore; in vlv_save_gunit_s0ix_state() local
115 s->wr_watermark = intel_uncore_read(uncore, GEN7_WR_WATERMARK); in vlv_save_gunit_s0ix_state()
116 s->gfx_prio_ctrl = intel_uncore_read(uncore, GEN7_GFX_PRIO_CTRL); in vlv_save_gunit_s0ix_state()
117 s->arb_mode = intel_uncore_read(uncore, ARB_MODE); in vlv_save_gunit_s0ix_state()
118 s->gfx_pend_tlb0 = intel_uncore_read(uncore, GEN7_GFX_PEND_TLB0); in vlv_save_gunit_s0ix_state()
119 s->gfx_pend_tlb1 = intel_uncore_read(uncore, GEN7_GFX_PEND_TLB1); in vlv_save_gunit_s0ix_state()
122 s->lra_limits[i] = intel_uncore_read(uncore, GEN7_LRA_LIMITS(i)); in vlv_save_gunit_s0ix_state()
124 s->media_max_req_count = intel_uncore_read(uncore, GEN7_MEDIA_MAX_REQ_COUNT); in vlv_save_gunit_s0ix_state()
125 s->gfx_max_req_count = intel_uncore_read(uncore, GEN7_GFX_MAX_REQ_COUNT); in vlv_save_gunit_s0ix_state()
127 s->render_hwsp = intel_uncore_read(uncore, RENDER_HWS_PGA_GEN7); in vlv_save_gunit_s0ix_state()
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| D | intel_uncore.h | 76 void (*force_wake_get)(struct intel_uncore *uncore,
78 void (*force_wake_put)(struct intel_uncore *uncore,
81 enum forcewake_domains (*read_fw_domains)(struct intel_uncore *uncore,
83 enum forcewake_domains (*write_fw_domains)(struct intel_uncore *uncore,
86 u8 (*mmio_readb)(struct intel_uncore *uncore,
88 u16 (*mmio_readw)(struct intel_uncore *uncore,
90 u32 (*mmio_readl)(struct intel_uncore *uncore,
92 u64 (*mmio_readq)(struct intel_uncore *uncore,
95 void (*mmio_writeb)(struct intel_uncore *uncore,
97 void (*mmio_writew)(struct intel_uncore *uncore,
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| D | i915_irq.h | 121 void gen2_irq_reset(struct intel_uncore *uncore);
122 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
125 void gen2_irq_init(struct intel_uncore *uncore,
127 void gen3_irq_init(struct intel_uncore *uncore,
132 #define GEN8_IRQ_RESET_NDX(uncore, type, which) \ argument
135 gen3_irq_reset((uncore), GEN8_##type##_IMR(which_), \
139 #define GEN3_IRQ_RESET(uncore, type) \ argument
140 gen3_irq_reset((uncore), type##IMR, type##IIR, type##IER)
142 #define GEN2_IRQ_RESET(uncore) \ argument
143 gen2_irq_reset(uncore)
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| D | i915_irq.c | 203 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr, in gen3_irq_reset() argument
206 intel_uncore_write(uncore, imr, 0xffffffff); in gen3_irq_reset()
207 intel_uncore_posting_read(uncore, imr); in gen3_irq_reset()
209 intel_uncore_write(uncore, ier, 0); in gen3_irq_reset()
212 intel_uncore_write(uncore, iir, 0xffffffff); in gen3_irq_reset()
213 intel_uncore_posting_read(uncore, iir); in gen3_irq_reset()
214 intel_uncore_write(uncore, iir, 0xffffffff); in gen3_irq_reset()
215 intel_uncore_posting_read(uncore, iir); in gen3_irq_reset()
218 void gen2_irq_reset(struct intel_uncore *uncore) in gen2_irq_reset() argument
220 intel_uncore_write16(uncore, GEN2_IMR, 0xffff); in gen2_irq_reset()
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| D | intel_sideband.c | 97 struct intel_uncore *uncore = &i915->uncore; in vlv_sideband_rw() local
106 if (intel_wait_for_register(uncore, in vlv_sideband_rw()
116 intel_uncore_write_fw(uncore, VLV_IOSF_ADDR, addr); in vlv_sideband_rw()
117 intel_uncore_write_fw(uncore, VLV_IOSF_DATA, is_read ? 0 : *val); in vlv_sideband_rw()
118 intel_uncore_write_fw(uncore, VLV_IOSF_DOORBELL_REQ, in vlv_sideband_rw()
126 if (__intel_wait_for_register_fw(uncore, in vlv_sideband_rw()
130 *val = intel_uncore_read_fw(uncore, VLV_IOSF_DATA); in vlv_sideband_rw()
292 struct intel_uncore *uncore = &i915->uncore; in intel_sbi_rw() local
297 if (intel_wait_for_register_fw(uncore, in intel_sbi_rw()
305 intel_uncore_write_fw(uncore, SBI_ADDR, (u32)reg << 16); in intel_sbi_rw()
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| D | i915_perf.c | 416 struct intel_uncore *uncore = stream->uncore; in gen12_oa_hw_tail_read() local
418 return intel_uncore_read(uncore, GEN12_OAG_OATAILPTR) & in gen12_oa_hw_tail_read()
424 struct intel_uncore *uncore = stream->uncore; in gen8_oa_hw_tail_read() local
426 return intel_uncore_read(uncore, GEN8_OATAILPTR) & GEN8_OATAILPTR_MASK; in gen8_oa_hw_tail_read()
431 struct intel_uncore *uncore = stream->uncore; in gen7_oa_hw_tail_read() local
432 u32 oastatus1 = intel_uncore_read(uncore, GEN7_OASTATUS1); in gen7_oa_hw_tail_read()
649 struct intel_uncore *uncore = stream->uncore; in gen8_append_oa_reports() local
660 if (drm_WARN_ON(&uncore->i915->drm, !stream->enabled)) in gen8_append_oa_reports()
684 if (drm_WARN_ONCE(&uncore->i915->drm, in gen8_append_oa_reports()
709 if (drm_WARN_ON(&uncore->i915->drm, in gen8_append_oa_reports()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/ |
| D | intel_rc6.c | 44 return rc6_to_gt(rc)->uncore; in rc6_to_uncore()
52 static inline void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val) in set() argument
54 intel_uncore_write_fw(uncore, reg, val); in set()
60 struct intel_uncore *uncore = gt->uncore; in gen11_rc6_enable() local
67 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85); in gen11_rc6_enable()
68 set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150); in gen11_rc6_enable()
70 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ in gen11_rc6_enable()
71 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ in gen11_rc6_enable()
73 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); in gen11_rc6_enable()
75 set(uncore, GUC_MAX_IDLE_COUNT, 0xA); in gen11_rc6_enable()
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| D | intel_gt_irq.c | 69 void __iomem * const regs = gt->uncore->regs; in gen11_gt_engine_identity()
154 void __iomem * const regs = gt->uncore->regs; in gen11_gt_bank_handler()
189 void __iomem * const regs = gt->uncore->regs; in gen11_gt_reset_one_iir()
218 struct intel_uncore *uncore = gt->uncore; in gen11_gt_irq_reset() local
221 intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0); in gen11_gt_irq_reset()
222 intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, 0); in gen11_gt_irq_reset()
225 intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~0); in gen11_gt_irq_reset()
226 intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~0); in gen11_gt_irq_reset()
227 intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~0); in gen11_gt_irq_reset()
228 intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~0); in gen11_gt_irq_reset()
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| D | intel_gtt.c | 239 struct intel_uncore *uncore = gt->uncore; in gtt_write_workarounds() local
248 intel_uncore_write(uncore, in gtt_write_workarounds()
252 intel_uncore_write(uncore, in gtt_write_workarounds()
256 intel_uncore_write(uncore, in gtt_write_workarounds()
260 intel_uncore_write(uncore, in gtt_write_workarounds()
277 intel_uncore_rmw(uncore, in gtt_write_workarounds()
295 intel_uncore_write(uncore, in gtt_write_workarounds()
299 intel_uncore_read(uncore, in gtt_write_workarounds()
304 static void tgl_setup_private_ppat(struct intel_uncore *uncore) in tgl_setup_private_ppat() argument
307 intel_uncore_write(uncore, GEN12_PAT_INDEX(0), GEN8_PPAT_WB); in tgl_setup_private_ppat()
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| D | debugfs_gt_pm.c | 24 struct intel_uncore *uncore = gt->uncore; in fw_domains_show() local
29 uncore->user_forcewake_count); in fw_domains_show()
31 for_each_fw_domain(fw_domain, uncore, tmp) in fw_domains_show()
47 with_intel_runtime_pm(gt->uncore->rpm, wakeref) in print_rc6_res()
49 intel_uncore_read(gt->uncore, reg), in print_rc6_res()
56 struct intel_uncore *uncore = gt->uncore; in vlv_drpc() local
59 pw_status = intel_uncore_read(uncore, VLV_GTLC_PW_STATUS); in vlv_drpc()
60 rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL); in vlv_drpc()
80 struct intel_uncore *uncore = gt->uncore; in gen6_drpc() local
84 gt_core_status = intel_uncore_read_fw(uncore, GEN6_GT_CORE_STATUS); in gen6_drpc()
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| D | intel_gt.c | 25 gt->uncore = &i915->uncore; in intel_gt_init_early()
59 struct intel_uncore *uncore = gt->uncore; in init_unused_ring() local
61 intel_uncore_write(uncore, RING_CTL(base), 0); in init_unused_ring()
62 intel_uncore_write(uncore, RING_HEAD(base), 0); in init_unused_ring()
63 intel_uncore_write(uncore, RING_TAIL(base), 0); in init_unused_ring()
64 intel_uncore_write(uncore, RING_START(base), 0); in init_unused_ring()
89 struct intel_uncore *uncore = gt->uncore; in intel_gt_init_hw() local
95 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); in intel_gt_init_hw()
98 intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf)); in intel_gt_init_hw()
101 intel_uncore_write(uncore, in intel_gt_init_hw()
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| D | intel_rps.c | 38 return rps_to_gt(rps)->uncore; in rps_to_uncore()
46 static inline void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val) in set() argument
48 intel_uncore_write_fw(uncore, reg, val); in set()
180 intel_uncore_write(gt->uncore, in rps_enable_interrupts()
213 intel_uncore_write(gt->uncore, in rps_disable_interrupts()
251 struct intel_uncore *uncore = rps_to_uncore(rps); in gen5_rps_init() local
271 rgvmodectl = intel_uncore_read(uncore, MEMMODECTL); in gen5_rps_init()
289 struct intel_uncore *uncore = in __ips_chipset_val() local
308 total = intel_uncore_read(uncore, DMIEC); in __ips_chipset_val()
309 total += intel_uncore_read(uncore, DDREC); in __ips_chipset_val()
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| D | intel_ggtt_fencing.c | 68 return fence->ggtt->vm.gt->uncore; in fence_to_uncore()
104 struct intel_uncore *uncore = fence_to_uncore(fence); in i965_write_fence_reg() local
116 intel_uncore_write_fw(uncore, fence_reg_lo, 0); in i965_write_fence_reg()
117 intel_uncore_posting_read_fw(uncore, fence_reg_lo); in i965_write_fence_reg()
119 intel_uncore_write_fw(uncore, fence_reg_hi, upper_32_bits(val)); in i965_write_fence_reg()
120 intel_uncore_write_fw(uncore, fence_reg_lo, lower_32_bits(val)); in i965_write_fence_reg()
121 intel_uncore_posting_read_fw(uncore, fence_reg_lo); in i965_write_fence_reg()
151 struct intel_uncore *uncore = fence_to_uncore(fence); in i915_write_fence_reg() local
154 intel_uncore_write_fw(uncore, reg, val); in i915_write_fence_reg()
155 intel_uncore_posting_read_fw(uncore, reg); in i915_write_fence_reg()
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| D | intel_gt_pm_irq.c | 16 struct intel_uncore *uncore = gt->uncore; in write_pm_imr() local
29 intel_uncore_write(uncore, reg, mask); in write_pm_imr()
64 struct intel_uncore *uncore = gt->uncore; in gen6_gt_pm_reset_iir() local
69 intel_uncore_write(uncore, reg, reset_mask); in gen6_gt_pm_reset_iir()
70 intel_uncore_write(uncore, reg, reset_mask); in gen6_gt_pm_reset_iir()
71 intel_uncore_posting_read(uncore, reg); in gen6_gt_pm_reset_iir()
77 struct intel_uncore *uncore = gt->uncore; in write_pm_ier() local
90 intel_uncore_write(uncore, reg, mask); in write_pm_ier()
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| D | intel_sseu_debugfs.c | 23 struct intel_uncore *uncore = gt->uncore; in cherryview_sseu_device_status() local
28 sig1[0] = intel_uncore_read(uncore, CHV_POWER_SS0_SIG1); in cherryview_sseu_device_status()
29 sig1[1] = intel_uncore_read(uncore, CHV_POWER_SS1_SIG1); in cherryview_sseu_device_status()
30 sig2[0] = intel_uncore_read(uncore, CHV_POWER_SS0_SIG2); in cherryview_sseu_device_status()
31 sig2[1] = intel_uncore_read(uncore, CHV_POWER_SS1_SIG2); in cherryview_sseu_device_status()
57 struct intel_uncore *uncore = gt->uncore; in gen10_sseu_device_status() local
69 s_reg[s] = intel_uncore_read(uncore, GEN10_SLICE_PGCTL_ACK(s)) & in gen10_sseu_device_status()
71 eu_reg[2 * s] = intel_uncore_read(uncore, in gen10_sseu_device_status()
73 eu_reg[2 * s + 1] = intel_uncore_read(uncore, in gen10_sseu_device_status()
117 struct intel_uncore *uncore = gt->uncore; in gen9_sseu_device_status() local
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| D | intel_reset.c | 32 static void rmw_set_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 set) in rmw_set_fw() argument
34 intel_uncore_rmw_fw(uncore, reg, 0, set); in rmw_set_fw()
37 static void rmw_clear_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 clr) in rmw_clear_fw() argument
39 intel_uncore_rmw_fw(uncore, reg, clr, 0); in rmw_clear_fw()
222 struct intel_uncore *uncore = gt->uncore; in g4x_do_reset() local
226 rmw_set_fw(uncore, VDECCLK_GATE_D, VCP_UNIT_CLOCK_GATE_DISABLE); in g4x_do_reset()
227 intel_uncore_posting_read_fw(uncore, VDECCLK_GATE_D); in g4x_do_reset()
248 rmw_clear_fw(uncore, VDECCLK_GATE_D, VCP_UNIT_CLOCK_GATE_DISABLE); in g4x_do_reset()
249 intel_uncore_posting_read_fw(uncore, VDECCLK_GATE_D); in g4x_do_reset()
257 struct intel_uncore *uncore = gt->uncore; in ilk_do_reset() local
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/uc/ |
| D | intel_guc_fw.c | 16 static void guc_prepare_xfer(struct intel_uncore *uncore) in guc_prepare_xfer() argument
26 intel_uncore_write(uncore, GUC_SHIM_CONTROL, shim_flags); in guc_prepare_xfer()
28 if (IS_GEN9_LP(uncore->i915)) in guc_prepare_xfer()
29 intel_uncore_write(uncore, GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE); in guc_prepare_xfer()
31 intel_uncore_write(uncore, GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE); in guc_prepare_xfer()
33 if (IS_GEN(uncore->i915, 9)) { in guc_prepare_xfer()
35 intel_uncore_rmw(uncore, GEN7_MISCCPCTL, in guc_prepare_xfer()
39 intel_uncore_write(uncore, GUC_ARAT_C6DIS, 0x1FF); in guc_prepare_xfer()
45 struct intel_uncore *uncore) in guc_xfer_rsa() argument
55 intel_uncore_write(uncore, UOS_RSA_SCRATCH(i), rsa[i]); in guc_xfer_rsa()
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| D | intel_guc.c | 45 intel_uncore_write(gt->uncore, guc->notify_reg, GUC_SEND_TRIGGER); in intel_guc_notify()
74 fw_domains |= intel_uncore_forcewake_for_reg(gt->uncore, in intel_guc_init_send_regs()
100 WARN_ON_ONCE(intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) & in gen9_enable_guc_interrupts()
143 intel_uncore_write(gt->uncore, in gen11_enable_guc_interrupts()
145 intel_uncore_write(gt->uncore, in gen11_enable_guc_interrupts()
159 intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_MASK, ~0); in gen11_disable_guc_interrupts()
160 intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_ENABLE, 0); in gen11_disable_guc_interrupts()
293 struct intel_uncore *uncore = guc_to_gt(guc)->uncore; in intel_guc_write_params() local
301 intel_uncore_forcewake_get(uncore, FORCEWAKE_BLITTER); in intel_guc_write_params()
303 intel_uncore_write(uncore, SOFT_SCRATCH(0), 0); in intel_guc_write_params()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/selftests/ |
| D | intel_uncore.c | 145 struct intel_uncore *uncore = gt->uncore; in live_forcewake_ops() local
181 wakeref = intel_runtime_pm_get(uncore->rpm); in live_forcewake_ops()
183 for_each_fw_domain(domain, uncore, tmp) { in live_forcewake_ops()
193 u32 __iomem *reg = uncore->regs + engine->mmio_base + r->offset; in live_forcewake_ops()
200 fw_domains = intel_uncore_forcewake_for_reg(uncore, mmio, in live_forcewake_ops()
205 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { in live_forcewake_ops()
215 intel_uncore_forcewake_get(uncore, fw_domains); in live_forcewake_ops()
217 intel_uncore_forcewake_put(uncore, fw_domains); in live_forcewake_ops()
220 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { in live_forcewake_ops()
252 intel_runtime_pm_put(uncore->rpm, wakeref); in live_forcewake_ops()
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| D | mock_uncore.c | 29 nop_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { }
36 nop_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { return 0; }
42 void mock_uncore_init(struct intel_uncore *uncore, in mock_uncore_init() argument
45 intel_uncore_init_early(uncore, i915); in mock_uncore_init()
47 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, nop); in mock_uncore_init()
48 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, nop); in mock_uncore_init()
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| /kernel/linux/linux-5.10/arch/x86/events/amd/ |
| D | uncore.c | 129 struct amd_uncore *uncore = event_to_amd_uncore(event); in amd_uncore_add() local
133 if (hwc->idx != -1 && uncore->events[hwc->idx] == event) in amd_uncore_add()
136 for (i = 0; i < uncore->num_counters; i++) { in amd_uncore_add()
137 if (uncore->events[i] == event) { in amd_uncore_add()
145 for (i = 0; i < uncore->num_counters; i++) { in amd_uncore_add()
146 if (cmpxchg(&uncore->events[i], NULL, event) == NULL) { in amd_uncore_add()
156 hwc->config_base = uncore->msr_base + (2 * hwc->idx); in amd_uncore_add()
157 hwc->event_base = uncore->msr_base + 1 + (2 * hwc->idx); in amd_uncore_add()
158 hwc->event_base_rdpmc = uncore->rdpmc_base + hwc->idx; in amd_uncore_add()
170 struct amd_uncore *uncore = event_to_amd_uncore(event); in amd_uncore_del() local
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gvt/ |
| D | aperture_gm.c | 133 struct intel_uncore *uncore = gvt->gt->uncore; in intel_vgpu_write_fence() local
137 assert_rpm_wakelock_held(uncore->rpm); in intel_vgpu_write_fence()
149 intel_uncore_write(uncore, fence_reg_lo, 0); in intel_vgpu_write_fence()
150 intel_uncore_posting_read(uncore, fence_reg_lo); in intel_vgpu_write_fence()
152 intel_uncore_write(uncore, fence_reg_hi, upper_32_bits(value)); in intel_vgpu_write_fence()
153 intel_uncore_write(uncore, fence_reg_lo, lower_32_bits(value)); in intel_vgpu_write_fence()
154 intel_uncore_posting_read(uncore, fence_reg_lo); in intel_vgpu_write_fence()
168 struct intel_uncore *uncore = gvt->gt->uncore; in free_vgpu_fence() local
176 wakeref = intel_runtime_pm_get(uncore->rpm); in free_vgpu_fence()
187 intel_runtime_pm_put(uncore->rpm, wakeref); in free_vgpu_fence()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gem/ |
| D | i915_gem_stolen.c | 74 struct intel_uncore *uncore = ggtt->vm.gt->uncore; in i915_adjust_stolen() local
92 ggtt_start = intel_uncore_read(uncore, PGTBL_CTL); in i915_adjust_stolen()
171 struct intel_uncore *uncore, in g4x_get_stolen_reserved() argument
175 u32 reg_val = intel_uncore_read(uncore, in g4x_get_stolen_reserved()
206 struct intel_uncore *uncore, in gen6_get_stolen_reserved() argument
210 u32 reg_val = intel_uncore_read(uncore, GEN6_STOLEN_RESERVED); in gen6_get_stolen_reserved()
239 struct intel_uncore *uncore, in vlv_get_stolen_reserved() argument
243 u32 reg_val = intel_uncore_read(uncore, GEN6_STOLEN_RESERVED); in vlv_get_stolen_reserved()
268 struct intel_uncore *uncore, in gen7_get_stolen_reserved() argument
272 u32 reg_val = intel_uncore_read(uncore, GEN6_STOLEN_RESERVED); in gen7_get_stolen_reserved()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/ |
| D | intel_de.h | 16 return intel_uncore_read(&i915->uncore, reg); in intel_de_read()
22 intel_uncore_posting_read(&i915->uncore, reg); in intel_de_posting_read()
29 return intel_uncore_read_fw(&i915->uncore, reg); in intel_de_read_fw()
35 intel_uncore_write(&i915->uncore, reg, val); in intel_de_write()
42 intel_uncore_write_fw(&i915->uncore, reg, val); in intel_de_write_fw()
48 intel_uncore_rmw(&i915->uncore, reg, clear, set); in intel_de_rmw()
55 return intel_wait_for_register(&i915->uncore, reg, mask, value, timeout); in intel_de_wait_for_register()
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