| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_ih.c | 75 unsigned wptr_offs, rptr_offs; in amdgpu_ih_ring_init() local
77 r = amdgpu_device_wb_get(adev, &wptr_offs); in amdgpu_ih_ring_init()
83 amdgpu_device_wb_free(adev, wptr_offs); in amdgpu_ih_ring_init()
93 amdgpu_device_wb_free(adev, wptr_offs); in amdgpu_ih_ring_init()
97 ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4; in amdgpu_ih_ring_init()
98 ih->wptr_cpu = &adev->wb.wb[wptr_offs]; in amdgpu_ih_ring_init()
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| D | amdgpu_ring.c | 202 r = amdgpu_device_wb_get(adev, &ring->wptr_offs); in amdgpu_ring_init()
294 amdgpu_device_wb_free(ring->adev, ring->wptr_offs); in amdgpu_ring_fini()
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| D | jpeg_v3_0.c | 422 return adev->wb.wb[ring->wptr_offs]; in jpeg_v3_0_dec_ring_get_wptr()
439 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in jpeg_v3_0_dec_ring_set_wptr()
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| D | jpeg_v2_5.c | 402 return adev->wb.wb[ring->wptr_offs]; in jpeg_v2_5_dec_ring_get_wptr()
419 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in jpeg_v2_5_dec_ring_set_wptr()
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| D | sdma_v5_2.c | 278 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); in sdma_v5_2_ring_get_wptr()
307 ring->wptr_offs, in sdma_v5_2_ring_set_wptr()
311 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2); in sdma_v5_2_ring_set_wptr()
312 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2); in sdma_v5_2_ring_set_wptr()
617 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in sdma_v5_2_gfx_resume()
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| D | vcn_v2_0.c | 1342 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_0_dec_ring_get_wptr()
1363 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_0_dec_ring_set_wptr()
1566 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_0_enc_ring_get_wptr()
1571 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_0_enc_ring_get_wptr()
1590 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_0_enc_ring_set_wptr()
1597 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_0_enc_ring_set_wptr()
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| D | vcn_v2_5.c | 1501 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_5_dec_ring_get_wptr()
1518 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_5_dec_ring_set_wptr()
1585 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_5_enc_ring_get_wptr()
1590 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_5_enc_ring_get_wptr()
1609 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_5_enc_ring_set_wptr()
1616 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_5_enc_ring_set_wptr()
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| D | sdma_v5_0.c | 329 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); in sdma_v5_0_ring_get_wptr()
358 ring->wptr_offs, in sdma_v5_0_ring_set_wptr()
362 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2); in sdma_v5_0_ring_set_wptr()
363 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2); in sdma_v5_0_ring_set_wptr()
687 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in sdma_v5_0_gfx_resume()
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| D | sdma_v4_0.c | 717 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); in sdma_v4_0_ring_get_wptr()
743 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; in sdma_v4_0_ring_set_wptr()
749 ring->wptr_offs, in sdma_v4_0_ring_set_wptr()
786 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); in sdma_v4_0_page_ring_get_wptr()
808 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; in sdma_v4_0_page_ring_set_wptr()
1194 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in sdma_v4_0_gfx_resume()
1285 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in sdma_v4_0_page_resume()
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| D | jpeg_v2_0.c | 430 return adev->wb.wb[ring->wptr_offs]; in jpeg_v2_0_dec_ring_get_wptr()
447 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in jpeg_v2_0_dec_ring_set_wptr()
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| D | mes_v10_1.c | 49 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], in mes_v10_1_ring_set_wptr()
68 &ring->adev->wb.wb[ring->wptr_offs]); in mes_v10_1_ring_get_wptr()
682 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in mes_v10_1_mqd_init()
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| D | sdma_v3_0.c | 370 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2; in sdma_v3_0_ring_get_wptr()
390 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs]; in sdma_v3_0_ring_set_wptr()
395 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs]; in sdma_v3_0_ring_set_wptr()
714 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in sdma_v3_0_gfx_resume()
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| D | vcn_v3_0.c | 1627 return adev->wb.wb[ring->wptr_offs]; in vcn_v3_0_dec_ring_get_wptr()
1644 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v3_0_dec_ring_set_wptr()
1711 return adev->wb.wb[ring->wptr_offs]; in vcn_v3_0_enc_ring_get_wptr()
1716 return adev->wb.wb[ring->wptr_offs]; in vcn_v3_0_enc_ring_get_wptr()
1735 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v3_0_enc_ring_set_wptr()
1742 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v3_0_enc_ring_set_wptr()
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| D | vce_v4_0.c | 85 return adev->wb.wb[ring->wptr_offs]; in vce_v4_0_ring_get_wptr()
108 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vce_v4_0_ring_set_wptr()
179 adev->wb.wb[adev->vce.ring[0].wptr_offs] = 0; in vce_v4_0_mmsch_start()
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| D | amdgpu_ring.h | 230 unsigned wptr_offs; member
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| D | uvd_v7_0.c | 121 return adev->wb.wb[ring->wptr_offs]; in uvd_v7_0_enc_ring_get_wptr()
156 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in uvd_v7_0_enc_ring_set_wptr()
738 adev->wb.wb[adev->uvd.inst[i].ring_enc[0].wptr_offs] = 0; in uvd_v7_0_mmsch_start()
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| D | gfx_v9_0.c | 835 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v9_0_kiq_map_queues()
3291 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v9_0_cp_gfx_resume()
3511 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v9_0_mqd_init()
3779 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); in gfx_v9_0_kcq_init_queue()
5215 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); in gfx_v9_0_ring_get_wptr_gfx()
5230 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr); in gfx_v9_0_ring_set_wptr_gfx()
5404 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); in gfx_v9_0_ring_get_wptr_compute()
5416 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr); in gfx_v9_0_ring_set_wptr_compute()
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| D | gfx_v10_0.c | 3238 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx10_kiq_map_queues()
5925 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v10_0_cp_gfx_resume()
5962 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v10_0_cp_gfx_resume()
6174 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v10_0_gfx_mqd_init()
6283 adev->wb.wb[ring->wptr_offs] = 0; in gfx_v10_0_gfx_init_queue()
6464 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v10_0_compute_mqd_init()
6684 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); in gfx_v10_0_kcq_init_queue()
7705 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); in gfx_v10_0_ring_get_wptr_gfx()
7720 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); in gfx_v10_0_ring_set_wptr_gfx()
7739 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); in gfx_v10_0_ring_get_wptr_compute()
[all …]
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| D | gfx_v8_0.c | 4305 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v8_0_cp_gfx_resume()
4388 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v8_0_kiq_kcq_enable()
4519 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v8_0_mqd_init()
6050 return ring->adev->wb.wb[ring->wptr_offs]; in gfx_v8_0_ring_get_wptr_gfx()
6061 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in gfx_v8_0_ring_set_wptr_gfx()
6261 return ring->adev->wb.wb[ring->wptr_offs]; in gfx_v8_0_ring_get_wptr_compute()
6269 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in gfx_v8_0_ring_set_wptr_compute()
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| D | gfx_v7_0.c | 2677 return ring->adev->wb.wb[ring->wptr_offs]; in gfx_v7_0_ring_get_wptr_compute()
2685 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in gfx_v7_0_ring_set_wptr_compute()
2981 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v7_0_mqd_init()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
| D | cik.c | 4174 wptr = rdev->wb.wb[ring->wptr_offs/4]; in cik_compute_get_wptr()
4190 rdev->wb.wb[ring->wptr_offs/4] = ring->wptr; in cik_compute_set_wptr()
8428 ring->wptr_offs = CIK_WB_CP1_WPTR_OFFSET; in cik_startup()
8440 ring->wptr_offs = CIK_WB_CP2_WPTR_OFFSET; in cik_startup()
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| D | radeon.h | 866 unsigned wptr_offs; member
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