| /third_party/mesa3d/src/amd/compiler/ |
| D | aco_validate.cpp | 84 aco::Instruction* instr) -> void in validate_ir()
94 aco_print_instr(instr, memf); in validate_ir()
114 for (aco_ptr<Instruction>& instr : block.instructions) { in validate_ir()
117 Format base_format = instr->format; in validate_ir()
127 if (instr->opcode == aco_opcode::v_interp_p1ll_f16 || in validate_ir()
128 instr->opcode == aco_opcode::v_interp_p1lv_f16 || in validate_ir()
129 instr->opcode == aco_opcode::v_interp_p2_legacy_f16 || in validate_ir()
130 instr->opcode == aco_opcode::v_interp_p2_f16) { in validate_ir()
139 check(base_format == instr_info.format[(int)instr->opcode], in validate_ir()
140 "Wrong base format for instruction", instr.get()); in validate_ir()
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| D | aco_optimizer.cpp | 39 perfwarn(Program* program, bool cond, const char* msg, Instruction* instr) in perfwarn() argument
49 aco_print_instr(instr, memf); in perfwarn()
81 mad_info(aco_ptr<Instruction> instr, uint32_t id) in mad_info()
82 : add_instr(std::move(instr)), mul_temp_id(id), literal_idx(0), check_literal(false) in mad_info()
148 Instruction* instr; member
187 instr = vec; in set_vec()
272 instr = mul; in set_mul()
289 instr = mad; in set_mad()
297 instr = mul; in set_omod2()
305 instr = mul; in set_omod4()
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| D | aco_insert_NOPs.cpp | 190 get_wait_states(aco_ptr<Instruction>& instr) in get_wait_states() argument
192 if (instr->opcode == aco_opcode::s_nop) in get_wait_states()
193 return instr->sopp().imm + 1; in get_wait_states()
194 else if (instr->opcode == aco_opcode::p_constaddr) in get_wait_states()
243 aco_ptr<Instruction>& instr = state.old_instructions[pred_idx]; in handle_raw_hazard_internal() local
244 if (!instr) in handle_raw_hazard_internal()
246 if (handle_raw_hazard_instr<Valu, Vintrp, Salu>(instr, reg, &nops_needed, &mask)) in handle_raw_hazard_internal()
324 handle_smem_clause_hazards(Program* program, NOP_ctx_gfx6& ctx, aco_ptr<Instruction>& instr, in handle_smem_clause_hazards() argument
331 if (ctx.smem_write || instr->definitions.empty() || in handle_smem_clause_hazards()
332 instr_info.is_atomic[(unsigned)instr->opcode]) { in handle_smem_clause_hazards()
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| D | aco_assembler.cpp | 65 get_mimg_nsa_dwords(const Instruction* instr) in get_mimg_nsa_dwords() argument
67 unsigned addr_dwords = instr->operands.size() - 3; in get_mimg_nsa_dwords()
69 if (instr->operands[3 + i].physReg() != instr->operands[3].physReg().advance(i * 4)) in get_mimg_nsa_dwords()
76 emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* instr) in emit_instruction() argument
79 if (instr->opcode == aco_opcode::p_constaddr_getpc) { in emit_instruction()
80 ctx.constaddrs[instr->operands[0].constantValue()].getpc_end = out.size() + 1; in emit_instruction()
82 instr->opcode = aco_opcode::s_getpc_b64; in emit_instruction()
83 instr->operands.pop_back(); in emit_instruction()
84 } else if (instr->opcode == aco_opcode::p_constaddr_addlo) { in emit_instruction()
85 ctx.constaddrs[instr->operands[1].constantValue()].add_literal = out.size() + 1; in emit_instruction()
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| /third_party/mesa3d/src/gallium/drivers/r600/sfn/ |
| D | sfn_emitaluinstruction.cpp | 45 const nir_alu_instr& instr = *nir_instr_as_alu(ir); in do_emit() local
47 r600::sfn_log << SfnLog::instr << "emit '" in do_emit()
49 << " bitsize: " << static_cast<int>(instr.dest.dest.ssa.bit_size) in do_emit()
52 preload_src(instr); in do_emit()
55 switch (instr.op) { in do_emit()
56 case nir_op_fcos_r600: return emit_alu_cm_trig(instr, op1_cos); in do_emit()
57 case nir_op_fexp2: return emit_alu_cm_trig(instr, op1_exp_ieee); in do_emit()
58 case nir_op_flog2: return emit_alu_cm_trig(instr, op1_log_clamped); in do_emit()
59 case nir_op_frcp: return emit_alu_cm_trig(instr, op1_recip_ieee); in do_emit()
60 case nir_op_frsq: return emit_alu_cm_trig(instr, op1_recipsqrt_ieee1); in do_emit()
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| D | sfn_emitaluinstruction.h | 52 bool do_emit(nir_instr* instr) override;
54 void split_constants(const nir_alu_instr& instr, unsigned nsrc_comp);
56 bool emit_mov(const nir_alu_instr& instr);
57 bool emit_alu_op1(const nir_alu_instr& instr, EAluOp opcode, const AluOpFlags &flags = 0);
58 bool emit_alu_op2(const nir_alu_instr& instr, EAluOp opcode, AluOp2Opts ops = op2_opt_none);
60 bool emit_alu_trans_op2(const nir_alu_instr& instr, EAluOp opcode);
61 bool emit_alu_cm_trig(const nir_alu_instr& instr, EAluOp opcode);
63 bool emit_alu_inot(const nir_alu_instr& instr);
64 bool emit_alu_ineg(const nir_alu_instr& instr);
65 bool emit_alu_op2_int(const nir_alu_instr& instr, EAluOp opcode, AluOp2Opts ops = op2_opt_none);
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| /third_party/mesa3d/src/gallium/drivers/lima/ir/gp/ |
| D | instr.c | 33 gpir_instr *instr = rzalloc(block, gpir_instr); in gpir_instr_create() local
34 if (unlikely(!instr)) in gpir_instr_create()
43 instr->index = block->sched.instr_index++; in gpir_instr_create()
44 instr->alu_num_slot_free = 6; in gpir_instr_create()
45 instr->alu_non_cplx_slot_free = 5; in gpir_instr_create()
46 instr->alu_max_allowed_next_max = 5; in gpir_instr_create()
48 list_add(&instr->list, &block->instr_list); in gpir_instr_create()
49 return instr; in gpir_instr_create()
52 static gpir_node *gpir_instr_get_the_other_acc_node(gpir_instr *instr, int slot) in gpir_instr_get_the_other_acc_node() argument
55 return instr->slots[GPIR_INSTR_SLOT_ADD1]; in gpir_instr_get_the_other_acc_node()
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| D | disasm.c | 50 print_dest(gpir_codegen_instr *instr, gp_unit unit, unsigned cur_dest_index, FILE *fp) in print_dest() argument
56 if (instr->store0_src_x == src || in print_dest()
57 instr->store0_src_y == src) { in print_dest()
58 if (instr->store0_temporary) { in print_dest()
64 if (instr->store0_varying) in print_dest()
68 fprintf(fp, "%u", instr->store0_addr); in print_dest()
72 if (instr->store0_src_x == src) in print_dest()
74 if (instr->store0_src_y == src) in print_dest()
78 if (instr->store1_src_z == src || in print_dest()
79 instr->store1_src_w == src) { in print_dest()
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| /third_party/mesa3d/src/freedreno/ir3/ |
| D | ir3_validate.c | 72 validate_src(struct ir3_validate_ctx *ctx, struct ir3_instruction *instr, in validate_src() argument
76 validate_assert(ctx, ir3_valid_immediate(instr, reg->iim_val)); in validate_src()
83 validate_assert(ctx, _mesa_set_search(ctx->defs, src->instr)); in validate_src()
90 foreach_dst (dst, instr) { in validate_src()
130 validate_dst(struct ir3_validate_ctx *ctx, struct ir3_instruction *instr, in validate_dst() argument
142 foreach_src (src, instr) { in validate_dst()
153 validate_assert(ctx, reg->instr == instr); in validate_dst()
156 validate_assert(ctx, instr->address); in validate_dst()
164 validate_instr(struct ir3_validate_ctx *ctx, struct ir3_instruction *instr) in validate_instr() argument
168 foreach_src_n (reg, n, instr) { in validate_instr()
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| D | ir3.c | 71 collect_reg_info(struct ir3_instruction *instr, struct ir3_register *reg, in collect_reg_info() argument
75 unsigned repeat = instr->repeat; in collect_reg_info()
235 foreach_instr (instr, &block->instr_list) { in ir3_collect_info()
252 foreach_instr (instr, &block->instr_list) { in ir3_collect_info()
254 foreach_src (reg, instr) { in ir3_collect_info()
255 collect_reg_info(instr, reg, info); in ir3_collect_info()
258 foreach_dst (reg, instr) { in ir3_collect_info()
260 collect_reg_info(instr, reg, info); in ir3_collect_info()
264 if ((instr->opc == OPC_STP || instr->opc == OPC_LDP)) { in ir3_collect_info()
265 unsigned components = instr->srcs[2]->uim_val; in ir3_collect_info()
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| D | ir3_sched.c | 45 #define di(instr, fmt, ...) \ argument
50 ir3_print_instr_stream(stream, instr); \
123 struct ir3_instruction *instr; member
169 struct ir3_instruction *instr);
170 static void sched_node_add_dep(struct ir3_instruction *instr,
174 is_scheduled(struct ir3_instruction *instr) in is_scheduled() argument
176 return !!(instr->flags & IR3_INSTR_MARK); in is_scheduled()
181 sched_check_src_cond(struct ir3_instruction *instr, in sched_check_src_cond() argument
186 foreach_ssa_src (src, instr) { in sched_check_src_cond()
205 is_outstanding_tex_or_prefetch(struct ir3_instruction *instr, in is_outstanding_tex_or_prefetch() argument
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| D | ir3_cp.c | 61 is_eligible_mov(struct ir3_instruction *instr, in is_eligible_mov() argument
64 if (is_same_type_mov(instr)) { in is_eligible_mov()
65 struct ir3_register *dst = instr->dsts[0]; in is_eligible_mov()
66 struct ir3_register *src = instr->srcs[0]; in is_eligible_mov()
107 (!cond->address || cond->address->def->instr->block == cmp->block); in is_foldable_double_cmp()
160 lower_immed(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr, unsigned n, in lower_immed() argument
169 if (!ir3_valid_flags(instr, n, new_flags)) in lower_immed()
178 (is_cat2_float(instr->opc) || is_cat3_float(instr->opc)) ? true : false; in lower_immed()
243 instr->srcs[n] = reg; in lower_immed()
249 unuse(struct ir3_instruction *instr) in unuse() argument
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| D | ir3_print.c | 70 print_instr_name(struct log_stream *stream, struct ir3_instruction *instr, in print_instr_name() argument
73 if (!instr) in print_instr_name()
76 mesa_log_stream_printf(stream, "%04u:", instr->serialno); in print_instr_name()
78 mesa_log_stream_printf(stream, "%04u:", instr->ip); in print_instr_name()
79 if (instr->flags & IR3_INSTR_UNUSED) { in print_instr_name()
82 mesa_log_stream_printf(stream, "%03u: ", instr->use_count); in print_instr_name()
87 if (instr->flags & IR3_INSTR_SY) in print_instr_name()
89 if (instr->flags & IR3_INSTR_SS) in print_instr_name()
91 if (instr->flags & IR3_INSTR_JP) in print_instr_name()
93 if (instr->repeat) in print_instr_name()
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| D | ir3_postsched.c | 46 #define di(instr, fmt, ...) \ argument
51 ir3_print_instr_stream(stream, instr); \
77 struct ir3_instruction *instr; member
90 has_tex_src(struct ir3_instruction *instr) in has_tex_src() argument
92 struct ir3_postsched_node *node = instr->data; in has_tex_src()
97 has_sfu_src(struct ir3_instruction *instr) in has_sfu_src() argument
99 struct ir3_postsched_node *node = instr->data; in has_sfu_src()
104 schedule(struct ir3_postsched_ctx *ctx, struct ir3_instruction *instr) in schedule() argument
106 debug_assert(ctx->block == instr->block); in schedule()
110 list_delinit(&instr->node); in schedule()
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| D | ir3_dce.c | 37 mark_array_use(struct ir3_instruction *instr, struct ir3_register *reg) in mark_array_use() argument
41 ir3_lookup_array(instr->block->shader, reg->array.id); in mark_array_use()
47 instr_dce(struct ir3_instruction *instr, bool falsedep) in instr_dce() argument
51 instr->flags &= ~IR3_INSTR_UNUSED; in instr_dce()
53 if (ir3_instr_check_mark(instr)) in instr_dce()
56 if (writes_gpr(instr)) in instr_dce()
57 mark_array_use(instr, instr->dsts[0]); /* dst */ in instr_dce()
59 foreach_src (reg, instr) in instr_dce()
60 mark_array_use(instr, reg); /* src */ in instr_dce()
62 foreach_ssa_src_n (src, i, instr) { in instr_dce()
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| /third_party/mesa3d/src/broadcom/qpu/ |
| D | qpu_disasm.c | 60 const struct v3d_qpu_instr *instr, uint8_t mux) in v3d_qpu_disasm_raddr() argument
63 append(disasm, "rf%d", instr->raddr_a); in v3d_qpu_disasm_raddr()
65 if (instr->sig.small_imm) { in v3d_qpu_disasm_raddr()
69 instr->raddr_b, in v3d_qpu_disasm_raddr()
78 append(disasm, "rf%d", instr->raddr_b); in v3d_qpu_disasm_raddr()
102 const struct v3d_qpu_instr *instr) in v3d_qpu_disasm_add() argument
104 bool has_dst = v3d_qpu_add_op_has_dst(instr->alu.add.op); in v3d_qpu_disasm_add()
105 int num_src = v3d_qpu_add_op_num_src(instr->alu.add.op); in v3d_qpu_disasm_add()
107 append(disasm, "%s", v3d_qpu_add_op_name(instr->alu.add.op)); in v3d_qpu_disasm_add()
108 if (!v3d_qpu_sig_writes_address(disasm->devinfo, &instr->sig)) in v3d_qpu_disasm_add()
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| D | qpu_pack.c | 743 struct v3d_qpu_instr *instr) in v3d_qpu_add_unpack() argument
766 instr->alu.add.op = desc->op; in v3d_qpu_add_unpack()
772 if (instr->alu.add.op == V3D_QPU_A_FMIN) in v3d_qpu_add_unpack()
773 instr->alu.add.op = V3D_QPU_A_FMAX; in v3d_qpu_add_unpack()
774 if (instr->alu.add.op == V3D_QPU_A_FADD) in v3d_qpu_add_unpack()
775 instr->alu.add.op = V3D_QPU_A_FADDNF; in v3d_qpu_add_unpack()
781 switch (instr->alu.add.op) { in v3d_qpu_add_unpack()
787 instr->alu.add.op = V3D_QPU_A_STVPMV; in v3d_qpu_add_unpack()
790 instr->alu.add.op = V3D_QPU_A_STVPMD; in v3d_qpu_add_unpack()
793 instr->alu.add.op = V3D_QPU_A_STVPMP; in v3d_qpu_add_unpack()
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| /third_party/mesa3d/src/gallium/drivers/freedreno/a2xx/ |
| D | ir2.c | 30 scalar_possible(struct ir2_instr *instr) in scalar_possible() argument
32 if (instr->alu.scalar_opc == SCALAR_NONE) in scalar_possible()
35 return src_ncomp(instr) == 1; in scalar_possible()
59 alu_vector_prio(struct ir2_instr *instr) in alu_vector_prio() argument
61 if (instr->alu.vector_opc == VECTOR_NONE) in alu_vector_prio()
64 if (is_export(instr)) in alu_vector_prio()
68 if (instr->src_count == 3) in alu_vector_prio()
71 if (!scalar_possible(instr)) in alu_vector_prio()
74 return instr->src_count == 2 ? 2 : 3; in alu_vector_prio()
79 alu_scalar_prio(struct ir2_instr *instr) in alu_scalar_prio() argument
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| D | ir2_nir.c | 250 reg = &ctx->instr[res.num].ssa; in make_src()
258 set_index(struct ir2_context *ctx, nir_dest *dst, struct ir2_instr *instr) in set_index() argument
260 struct ir2_reg *reg = &instr->ssa; in set_index()
263 ctx->ssa_map[dst->ssa.index] = instr->idx; in set_index()
265 assert(instr->is_ssa); in set_index()
268 instr->is_ssa = false; in set_index()
269 instr->reg = reg; in set_index()
277 struct ir2_instr *instr; in ir2_instr_create() local
279 instr = &ctx->instr[ctx->instr_count++]; in ir2_instr_create()
280 instr->idx = ctx->instr_count - 1; in ir2_instr_create()
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| /third_party/mesa3d/src/freedreno/isa/ |
| D | encode.c | 40 struct ir3_instruction *instr; member
49 extract_SRC1_R(struct ir3_instruction *instr) in extract_SRC1_R() argument
51 if (instr->nop) { in extract_SRC1_R()
52 assert(!instr->repeat); in extract_SRC1_R()
53 return instr->nop & 0x1; in extract_SRC1_R()
55 return !!(instr->srcs[0]->flags & IR3_REG_R); in extract_SRC1_R()
59 extract_SRC2_R(struct ir3_instruction *instr) in extract_SRC2_R() argument
61 if (instr->nop) { in extract_SRC2_R()
62 assert(!instr->repeat); in extract_SRC2_R()
63 return (instr->nop >> 1) & 0x1; in extract_SRC2_R()
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| /third_party/mesa3d/src/gallium/drivers/zink/ |
| D | nir_lower_dynamic_bo_access.c | 45 recursive_generate_bo_ssa_def(nir_builder *b, nir_intrinsic_instr *instr, nir_ssa_def *index, unsig… in recursive_generate_bo_ssa_def() argument
48 nir_intrinsic_instr *new_instr = nir_intrinsic_instr_create(b->shader, instr->intrinsic); in recursive_generate_bo_ssa_def()
50 for (unsigned i = 0; i < nir_intrinsic_infos[instr->intrinsic].num_srcs; i++) { in recursive_generate_bo_ssa_def()
52 nir_src_copy(&new_instr->src[i], &instr->src[i]); in recursive_generate_bo_ssa_def()
54 if (instr->intrinsic != nir_intrinsic_load_ubo_vec4) { in recursive_generate_bo_ssa_def()
55 …_intrinsic_set_align(new_instr, nir_intrinsic_align_mul(instr), nir_intrinsic_align_offset(instr)); in recursive_generate_bo_ssa_def()
56 if (instr->intrinsic != nir_intrinsic_load_ssbo) in recursive_generate_bo_ssa_def()
57 nir_intrinsic_set_range(new_instr, nir_intrinsic_range(instr)); in recursive_generate_bo_ssa_def()
59 new_instr->num_components = instr->num_components; in recursive_generate_bo_ssa_def()
60 nir_ssa_dest_init(&new_instr->instr, &new_instr->dest, in recursive_generate_bo_ssa_def()
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| /third_party/mesa3d/src/compiler/nir/ |
| D | nir_search_helpers.h | 36 is_pos_power_of_two(UNUSED struct hash_table *ht, const nir_alu_instr *instr, in is_pos_power_of_two() argument
41 if (!nir_src_is_const(instr->src[src].src)) in is_pos_power_of_two()
45 nir_alu_type type = nir_op_infos[instr->op].input_types[src]; in is_pos_power_of_two()
48 int64_t val = nir_src_comp_as_int(instr->src[src].src, swizzle[i]); in is_pos_power_of_two()
54 uint64_t val = nir_src_comp_as_uint(instr->src[src].src, swizzle[i]); in is_pos_power_of_two()
68 is_neg_power_of_two(UNUSED struct hash_table *ht, const nir_alu_instr *instr, in is_neg_power_of_two() argument
73 if (!nir_src_is_const(instr->src[src].src)) in is_neg_power_of_two()
76 int64_t int_min = u_intN_min(instr->src[src].src.ssa->bit_size); in is_neg_power_of_two()
79 nir_alu_type type = nir_op_infos[instr->op].input_types[src]; in is_neg_power_of_two()
82 int64_t val = nir_src_comp_as_int(instr->src[src].src, swizzle[i]); in is_neg_power_of_two()
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| D | nir_opt_shrink_vectors.c | 74 opt_shrink_vectors_alu(nir_builder *b, nir_alu_instr *instr) in opt_shrink_vectors_alu() argument
76 nir_ssa_def *def = &instr->dest.dest.ssa; in opt_shrink_vectors_alu()
83 switch (instr->op) { in opt_shrink_vectors_alu()
91 if (nir_op_infos[instr->op].output_size != 0) in opt_shrink_vectors_alu()
118 srcs[index++] = nir_ssa_for_alu_src(b, instr, i); in opt_shrink_vectors_alu()
129 instr->dest.write_mask = mask; in opt_shrink_vectors_alu()
135 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) { in opt_shrink_vectors_alu()
139 instr->src[i].swizzle[index++] = instr->src[i].swizzle[j]; in opt_shrink_vectors_alu()
146 instr->dest.write_mask = BITFIELD_MASK(num_components); in opt_shrink_vectors_alu()
170 opt_shrink_vectors_image_store(nir_builder *b, nir_intrinsic_instr *instr) in opt_shrink_vectors_image_store() argument
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| D | nir_opt_gcm.c | 79 nir_instr *instr; member
104 nir_foreach_instr(instr, block) { in get_loop_instr_count()
243 nir_instr *instr = &intrin->instr; in pin_intrinsic() local
246 instr->pass_flags = GCM_INSTR_PINNED; in pin_intrinsic()
250 instr->pass_flags = 0; in pin_intrinsic()
269 instr->pass_flags = GCM_INSTR_PINNED; in pin_intrinsic()
272 instr->pass_flags = GCM_INSTR_PINNED; in pin_intrinsic()
281 instr->pass_flags = GCM_INSTR_PINNED; in pin_intrinsic()
286 instr->pass_flags = GCM_INSTR_PINNED; in pin_intrinsic()
306 nir_foreach_instr_safe(instr, block) { in gcm_pin_instructions()
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| /third_party/mesa3d/src/broadcom/compiler/ |
| D | v3d40_tex.c | 84 nir_tex_instr *instr, in handle_tex_src() argument
97 switch (instr->src[src_idx].src_type) { in handle_tex_src()
100 s = ntq_get_src(c, instr->src[src_idx].src, 0); in handle_tex_src()
108 ntq_get_src(c, instr->src[src_idx].src, 1); in handle_tex_src()
115 ntq_get_src(c, instr->src[src_idx].src, 2); in handle_tex_src()
120 if (instr->is_array) { in handle_tex_src()
122 ntq_get_src(c, instr->src[src_idx].src, in handle_tex_src()
123 instr->coord_components - 1); in handle_tex_src()
130 struct qreg src = ntq_get_src(c, instr->src[src_idx].src, 0); in handle_tex_src()
136 struct qreg src = ntq_get_src(c, instr->src[src_idx].src, 0); in handle_tex_src()
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