| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64ExternalSymbolizer.cpp | 108 MI.getOpcode() == AArch64::ADR) { in tryAddingSymbolicOperand()
117 } else if (MI.getOpcode() == AArch64::ADR) { in tryAddingSymbolicOperand()
|
| /third_party/boost/libs/context/src/asm/ |
| D | make_arm64_aapcs_macho_gas.S | 72 ; TODO: Numeric offset since llvm still does not support labels in ADR. Fix:
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedPredExynos.td | 125 [ADR, ADRP,
|
| D | AArch64MacroFusion.cpp | 219 case AArch64::ADR: in isAddressLdStPair()
|
| D | AArch64ISelLowering.h | 37 ADR, // ADR enumerator
|
| D | AArch64AsmPrinter.cpp | 841 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::ADR) in LowerJumpTableDestSmall()
|
| D | AArch64SchedCyclone.td | 138 // ADR,ADRP
|
| D | AArch64SchedExynosM3.td | 505 def : InstRW<[M3WriteZ0], (instrs ADR, ADRP)>;
|
| D | AArch64SchedExynosM4.td | 602 def : InstRW<[M4WriteZ0], (instrs ADR, ADRP)>;
|
| D | AArch64SchedExynosM5.td | 649 def : InstRW<[M5WriteZ0], (instrs ADR, ADRP)>;
|
| D | AArch64InstrInfo.td | 373 def AArch64adr : SDNode<"AArch64ISD::ADR", SDTIntUnaryOp, []>;
1873 def ADR : ADRI<0, "adr", adrlabel,
1882 def : Pat<(AArch64adr tconstpool:$cp), (ADR tconstpool:$cp)>;
1883 def : Pat<(AArch64adr tblockaddress:$cp), (ADR tblockaddress:$cp)>;
1884 def : Pat<(AArch64adr texternalsym:$sym), (ADR texternalsym:$sym)>;
1885 def : Pat<(AArch64adr tjumptable:$sym), (ADR tjumptable:$sym)>;
|
| D | AArch64SchedKryoDetails.td | 351 (instregex "ADR.*")>;
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/ |
| D | LoopRerollPass.cpp | 892 const auto *ADR = dyn_cast<SCEVAddRecExpr>(SE->getSCEV(DRS.BaseInst)); in validateRootSet() local
893 if (!ADR) in validateRootSet()
898 const SCEV *StepSCEV = SE->getMinusSCEV(SE->getSCEV(DRS.Roots[0]), ADR); in validateRootSet()
900 if (ADR->getStepRecurrence(*SE) != SE->getMulExpr(StepSCEV, ScaleSCEV)) in validateRootSet()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64MCCodeEmitter.cpp | 244 MCFixupKind Kind = MI.getOpcode() == AArch64::ADR in getAdrLabelOpValue()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrHFP.td | 134 def ADR : BinaryRR<"adr", 0x2A, null_frag, FP64, FP64>;
|
| /third_party/cmsis/CMSIS/Core/Include/ |
| D | core_sc300.h | 397 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ member
|
| D | core_cm3.h | 397 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ member
|
| D | core_cm4.h | 463 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ member
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMAsmPrinter.cpp | 1284 : ARM::ADR)) in EmitInstruction()
1300 : ARM::ADR)) in EmitInstruction()
|
| D | ARMScheduleR52.td | 326 (instregex "ADR", "MOVsi", "MVNS?s?i", "t2MOVS?si")>;
|
| D | ARMScheduleSwift.td | 129 // ADC,ADD,NEG,RSB,RSC,SBC,SUB,ADR
|
| D | ARMScheduleA57.td | 183 // ADD{S}, ADC{S}, ADR, AND{S}, BIC{S}, CMN, CMP, EOR{S}, ORN{S}, ORR{S},
|
| D | ARMInstrThumb.td | 129 // ADR instruction labels.
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmWriter.inc | 1315 3174515U, // ADR
5539 1280U, // ADR
9424 // ADCri, ADCrr, ADCrsi, ADDri, ADDrr, ADDrsi, ADR, ANDri, ANDrr, ANDrsi,...
10533 // ADR, t2ADR
|
| D | ARMGenSubtargetInfo.inc | 5539 { 1, 1, 2, 898, 900 }, // 707 ADR
6586 { 1, 13, 15, 3381, 3383 }, // 707 ADR
7633 { 1, 265, 266, 6376, 6378 }, // 707 ADR
11455 {DBGFIELD("ADR") 1, false, false, 1, 1, 1, 1, 1, 21}, // #707
12904 {DBGFIELD("ADR") 1, false, false, 1, 1, 1, 1, 0, 1}, // #707
14353 {DBGFIELD("ADR") 1, false, false, 3, 1, 1, 1, 0, 1}, // #707
15802 {DBGFIELD("ADR") 1, false, false, 3, 1, 2, 1, 0, 0}, // #707
17251 {DBGFIELD("ADR") 1, false, false, 4, 1, 1, 1, 0, 1}, // #707
|