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Searched refs:ARM (Results 1 – 25 of 732) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp153 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
154 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
155 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
156 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
157 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
158 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
160 { ARM::VLD1d16QPseudo, ARM::VLD1d16Q, true, false, false, SingleSpc, 4, 4 ,false},
161 { ARM::VLD1d16TPseudo, ARM::VLD1d16T, true, false, false, SingleSpc, 3, 4 ,false},
162 { ARM::VLD1d32QPseudo, ARM::VLD1d32Q, true, false, false, SingleSpc, 4, 2 ,false},
163 { ARM::VLD1d32TPseudo, ARM::VLD1d32T, true, false, false, SingleSpc, 3, 2 ,false},
[all …]
DARMFeatures.h28 case ARM::tADC: in isV8EligibleForIT()
29 case ARM::tADDi3: in isV8EligibleForIT()
30 case ARM::tADDi8: in isV8EligibleForIT()
31 case ARM::tADDrr: in isV8EligibleForIT()
32 case ARM::tAND: in isV8EligibleForIT()
33 case ARM::tASRri: in isV8EligibleForIT()
34 case ARM::tASRrr: in isV8EligibleForIT()
35 case ARM::tBIC: in isV8EligibleForIT()
36 case ARM::tEOR: in isV8EligibleForIT()
37 case ARM::tLSLri: in isV8EligibleForIT()
[all …]
DARMBaseInstrInfo.cpp89 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
90 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
91 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
92 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
93 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
94 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
95 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
96 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
99 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
100 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
[all …]
DARMRegisterBankInfo.cpp30 namespace ARM { namespace
144 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID); in ARMRegisterBankInfo()
146 assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up"); in ARMRegisterBankInfo()
149 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) && in ARMRegisterBankInfo()
151 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) && in ARMRegisterBankInfo()
153 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) && in ARMRegisterBankInfo()
155 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) && in ARMRegisterBankInfo()
157 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) && in ARMRegisterBankInfo()
159 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) && in ARMRegisterBankInfo()
161 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPR_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
[all …]
DThumb2SizeReduction.cpp83 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0,0 },
84 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1,0 },
85 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0,0 },
86 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1,0 },
87 { ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 0,1,0 },
88 { ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 1,0,0 },
89 { ARM::t2ASRri, ARM::tASRri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
90 { ARM::t2ASRrr, 0, ARM::tASRrr, 0, 0, 0, 1, 0,0, 1,0,1 },
91 { ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 1,0,0 },
94 { ARM::t2CMNzrr, ARM::tCMNz, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
[all …]
DThumb2InstrInfo.cpp46 NopInst.setOpcode(ARM::tHINT); in getNoop()
88 if (MBBI->getOpcode() == ARM::t2IT) { in ReplaceTailWithBranchTo()
126 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
129 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
148 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
149 BuildMI(MBB, I, DL, get(ARM::t2STRi12)) in storeRegToStackSlot()
158 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
164 MRI->constrainRegClass(SrcReg, &ARM::GPRPairnospRegClass); in storeRegToStackSlot()
167 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8)); in storeRegToStackSlot()
168 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
[all …]
DARMInstrInfo.cpp37 NopInst.setOpcode(ARM::HINT); in getNoop()
42 NopInst.setOpcode(ARM::MOVr); in getNoop()
43 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNoop()
44 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNoop()
55 case ARM::LDR_PRE_IMM: in getUnindexedOpcode()
56 case ARM::LDR_PRE_REG: in getUnindexedOpcode()
57 case ARM::LDR_POST_IMM: in getUnindexedOpcode()
58 case ARM::LDR_POST_REG: in getUnindexedOpcode()
59 return ARM::LDRi12; in getUnindexedOpcode()
60 case ARM::LDRH_PRE: in getUnindexedOpcode()
[all …]
DARMTargetTransformInfo.h57 ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureNEON, ARM::FeatureThumb2,
58 ARM::FeatureFP16, ARM::FeatureVFP4, ARM::FeatureFPARMv8,
59 ARM::FeatureFullFP16, ARM::FeatureFP16FML, ARM::FeatureHWDivThumb,
60 ARM::FeatureHWDivARM, ARM::FeatureDB, ARM::FeatureV7Clrex,
61 ARM::FeatureAcquireRelease, ARM::FeatureSlowFPBrcc,
62 ARM::FeaturePerfMon, ARM::FeatureTrustZone, ARM::Feature8MSecExt,
63 ARM::FeatureCrypto, ARM::FeatureCRC, ARM::FeatureRAS,
64 ARM::FeatureFPAO, ARM::FeatureFuseAES, ARM::FeatureZCZeroing,
65 ARM::FeatureProfUnpredicate, ARM::FeatureSlowVGETLNi32,
66 ARM::FeatureSlowVDUP32, ARM::FeaturePreferVMOVSR,
[all …]
DARMBaseInstrInfo.h481 return MachineOperand::CreateReg(ARM::CPSR,
488 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B; in isUncondBranchOpcode()
513 return Opc == ARM::MVE_VPTv16i8 || Opc == ARM::MVE_VPTv16u8 || in isVPTOpcode()
514 Opc == ARM::MVE_VPTv16s8 || Opc == ARM::MVE_VPTv8i16 || in isVPTOpcode()
515 Opc == ARM::MVE_VPTv8u16 || Opc == ARM::MVE_VPTv8s16 || in isVPTOpcode()
516 Opc == ARM::MVE_VPTv4i32 || Opc == ARM::MVE_VPTv4u32 || in isVPTOpcode()
517 Opc == ARM::MVE_VPTv4s32 || Opc == ARM::MVE_VPTv4f32 || in isVPTOpcode()
518 Opc == ARM::MVE_VPTv8f16 || Opc == ARM::MVE_VPTv16i8r || in isVPTOpcode()
519 Opc == ARM::MVE_VPTv16u8r || Opc == ARM::MVE_VPTv16s8r || in isVPTOpcode()
520 Opc == ARM::MVE_VPTv8i16r || Opc == ARM::MVE_VPTv8u16r || in isVPTOpcode()
[all …]
DARMLoadStoreOptimizer.cpp207 if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead()) in definesCPSR()
218 bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD; in getMemoryOpOffset()
222 if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 || in getMemoryOpOffset()
223 Opcode == ARM::t2STRi12 || Opcode == ARM::t2STRi8 || in getMemoryOpOffset()
224 Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8 || in getMemoryOpOffset()
225 Opcode == ARM::LDRi12 || Opcode == ARM::STRi12) in getMemoryOpOffset()
229 if (Opcode == ARM::tLDRi || Opcode == ARM::tSTRi || in getMemoryOpOffset()
230 Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) in getMemoryOpOffset()
255 case ARM::LDRi12: in getLoadStoreMultipleOpcode()
259 case ARM_AM::ia: return ARM::LDMIA; in getLoadStoreMultipleOpcode()
[all …]
DThumb1FrameLowering.cpp79 if (ScratchReg == ARM::NoRegister) in emitPrologueEpilogueSPUpdate()
84 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ScratchReg) in emitPrologueEpilogueSPUpdate()
90 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDhirr), ARM::SP) in emitPrologueEpilogueSPUpdate()
91 .addReg(ARM::SP).addReg(ScratchReg, RegState::Kill) in emitPrologueEpilogueSPUpdate()
97 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, in emitPrologueEpilogueSPUpdate()
107 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, in emitCallSPUpdate()
134 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { in eliminateCallFramePseudoInstr()
137 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); in eliminateCallFramePseudoInstr()
182 ARM::NoRegister, MachineInstr::FrameSetup); in emitPrologue()
195 ARM::NoRegister, MachineInstr::FrameSetup); in emitPrologue()
[all …]
DARMCallingConv.cpp24 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS()
67 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64AssignAAPCS()
68 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64AssignAAPCS()
69 static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 }; in f64AssignAAPCS()
70 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS()
77 assert((!Reg || Reg == ARM::R3) && "Wrong GPRs usage for f64"); in f64AssignAAPCS()
119 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64RetAssign()
120 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64RetAssign()
156 static const MCPhysReg RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
158 static const MCPhysReg SRegList[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3,
[all …]
DARMISelDAGToDAG.cpp108 Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32); in SelectCMOVPred()
479 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasNoVMLxHazardUse()
1534 Opcode = ARM::LDR_PRE_IMM; in tryARMIndexedLoad()
1538 Opcode = ARM::LDR_POST_IMM; in tryARMIndexedLoad()
1542 Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG; in tryARMIndexedLoad()
1549 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST) in tryARMIndexedLoad()
1550 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST); in tryARMIndexedLoad()
1555 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST; in tryARMIndexedLoad()
1561 Opcode = ARM::LDRB_PRE_IMM; in tryARMIndexedLoad()
1565 Opcode = ARM::LDRB_POST_IMM; in tryARMIndexedLoad()
[all …]
DARMFrameLowering.cpp156 if ((MI.getOpcode() == ARM::LDR_POST_IMM || in isCSRestore()
157 MI.getOpcode() == ARM::LDR_POST_REG || in isCSRestore()
158 MI.getOpcode() == ARM::t2LDR_POST) && in isCSRestore()
160 MI.getOperand(1).getReg() == ARM::SP) in isCSRestore()
185 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes, in emitSPUpdate()
192 case ARM::VSTMDDB_UPD: in sizeOfSPAdjustment()
195 case ARM::STMDB_UPD: in sizeOfSPAdjustment()
196 case ARM::t2STMDB_UPD: in sizeOfSPAdjustment()
199 case ARM::t2STR_PRE: in sizeOfSPAdjustment()
200 case ARM::STR_PRE_IMM: in sizeOfSPAdjustment()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DARMTargetParser.def1 //===- ARMTargetParser.def - ARM target parsing defines ---------*- C++ -*-===//
9 // This file provides defines to build up the ARM target parser's logic.
49 ARMBuildAttrs::CPUArch::Pre_v4, FK_NONE, ARM::AEK_NONE)
51 FK_NONE, ARM::AEK_NONE)
53 FK_NONE, ARM::AEK_NONE)
55 FK_NONE, ARM::AEK_NONE)
57 FK_NONE, ARM::AEK_NONE)
59 FK_NONE, ARM::AEK_NONE)
61 FK_NONE, ARM::AEK_NONE)
63 FK_NONE, ARM::AEK_NONE)
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-subzero/include/llvm/Support/
DARMTargetParser.def1 //===- ARMTargetParser.def - ARM target parsing defines ---------*- C++ -*-===//
10 // This file provides defines to build up the ARM target parser's logic.
48 ARMBuildAttrs::CPUArch::Pre_v4, FK_NONE, ARM::AEK_NONE)
50 FK_NONE, ARM::AEK_NONE)
52 FK_NONE, ARM::AEK_NONE)
54 FK_NONE, ARM::AEK_NONE)
56 FK_NONE, ARM::AEK_NONE)
58 FK_NONE, ARM::AEK_NONE)
60 FK_NONE, ARM::AEK_NONE)
62 FK_NONE, ARM::AEK_NONE)
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenRegisterInfo.inc18 namespace ARM {
317 } // end namespace ARM
321 namespace ARM {
447 } // end namespace ARM
452 namespace ARM {
458 } // end namespace ARM
463 namespace ARM {
524 } // end namespace ARM
1479 { ARM::APSR },
1480 { ARM::APSR_NZCV },
[all …]
DARMGenRegisterBank.inc12 namespace ARM {
18 } // end namespace ARM
35 namespace ARM {
38 (1u << (ARM::HPRRegClassID - 0)) |
39 (1u << (ARM::SPRRegClassID - 0)) |
40 (1u << (ARM::SPR_8RegClassID - 0)) |
41 (1u << (ARM::FPWithVPRRegClassID - 0)) |
42 (1u << (ARM::FPWithVPR_with_ssub_0RegClassID - 0)) |
43 (1u << (ARM::FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClassID - 0)) |
46 (1u << (ARM::DPRRegClassID - 32)) |
[all …]
DARMGenMCCodeEmitter.inc4241 case ARM::CLREX:
4242 case ARM::MVE_LCTP:
4243 case ARM::MVE_VPNOT:
4244 case ARM::SB:
4245 case ARM::TRAP:
4246 case ARM::TRAPNaCl:
4247 case ARM::TSB:
4248 case ARM::VLD1LNq16Pseudo:
4249 case ARM::VLD1LNq16Pseudo_UPD:
4250 case ARM::VLD1LNq32Pseudo:
[all …]
DARMGenAsmMatcher.inc648 case Feature_HasDivideInARMBit: return "divide in ARM";
4398 Inst.addOperand(MCOperand::createReg(ARM::SP));
4461 Inst.addOperand(MCOperand::createReg(ARM::ZR));
4572 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
4587 Inst.addOperand(MCOperand::createReg(ARM::R8));
4590 Inst.addOperand(MCOperand::createReg(ARM::R0));
7856 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<0,ARM::GPRnopcRegClassID>());
7863 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<0,ARM::rGPRRegClassID>());
7870 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<1,ARM::GPRnopcRegClassID>());
7877 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<1,ARM::rGPRRegClassID>());
[all …]
DARMGenCallingConv.inc57 if (unsigned Reg = State.AllocateReg(ARM::R12)) {
85 if (unsigned Reg = State.AllocateReg(ARM::R10)) {
94 if (unsigned Reg = State.AllocateReg(ARM::R8)) {
138 ARM::R0, ARM::R2
141 ARM::R0, ARM::R1
153 ARM::R0, ARM::R1, ARM::R2, ARM::R3
165 ARM::R0, ARM::R1, ARM::R2, ARM::R3
175 ARM::R0, ARM::R1, ARM::R2, ARM::R3
184 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
193 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/
DARMTargetStreamer.cpp110 void ARMTargetStreamer::emitArch(ARM::ArchKind Arch) {} in emitArch()
112 void ARMTargetStreamer::emitObjectArch(ARM::ArchKind Arch) {} in emitObjectArch()
123 if (STI.hasFeature(ARM::HasV8Ops)) { in getArchForCPU()
124 if (STI.hasFeature(ARM::FeatureRClass)) in getArchForCPU()
127 } else if (STI.hasFeature(ARM::HasV8_1MMainlineOps)) in getArchForCPU()
129 else if (STI.hasFeature(ARM::HasV8MMainlineOps)) in getArchForCPU()
131 else if (STI.hasFeature(ARM::HasV7Ops)) { in getArchForCPU()
132 if (STI.hasFeature(ARM::FeatureMClass) && STI.hasFeature(ARM::FeatureDSP)) in getArchForCPU()
135 } else if (STI.hasFeature(ARM::HasV6T2Ops)) in getArchForCPU()
137 else if (STI.hasFeature(ARM::HasV8MBaselineOps)) in getArchForCPU()
[all …]
DARMAsmBackend.cpp60 const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = { in getFixupKindInfo()
114 const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = { in getFixupKindInfo()
197 bool HasThumb2 = STI.getFeatureBits()[ARM::FeatureThumb2]; in getRelaxedOpcode()
198 bool HasV8MBaselineOps = STI.getFeatureBits()[ARM::HasV8MBaselineOps]; in getRelaxedOpcode()
203 case ARM::tBcc: in getRelaxedOpcode()
204 return HasThumb2 ? (unsigned)ARM::t2Bcc : Op; in getRelaxedOpcode()
205 case ARM::tLDRpci: in getRelaxedOpcode()
206 return HasThumb2 ? (unsigned)ARM::t2LDRpci : Op; in getRelaxedOpcode()
207 case ARM::tADR: in getRelaxedOpcode()
208 return HasThumb2 ? (unsigned)ARM::t2ADR : Op; in getRelaxedOpcode()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp586 case ARM::HVC: { in checkDecodedInstruction()
596 case ARM::t2ADDri: in checkDecodedInstruction()
597 case ARM::t2ADDri12: in checkDecodedInstruction()
598 case ARM::t2ADDrr: in checkDecodedInstruction()
599 case ARM::t2ADDrs: in checkDecodedInstruction()
600 case ARM::t2SUBri: in checkDecodedInstruction()
601 case ARM::t2SUBri12: in checkDecodedInstruction()
602 case ARM::t2SUBrr: in checkDecodedInstruction()
603 case ARM::t2SUBrs: in checkDecodedInstruction()
604 if (MI.getOperand(0).getReg() == ARM::SP && in checkDecodedInstruction()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp120 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {} in UnwindContext()
179 FPReg = ARM::SP; in reset()
245 ITInst.setOpcode(ARM::t2IT); in flushPendingInstructions()
302 return MRI->getSubReg(QReg, ARM::dsub_0); in getDRegFromQReg()
449 return getSTI().getFeatureBits()[ARM::ModeThumb]; in isThumb()
453 return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2]; in isThumbOne()
457 return isThumb() && getSTI().getFeatureBits()[ARM::FeatureThumb2]; in isThumbTwo()
461 return getSTI().getFeatureBits()[ARM::HasV4TOps]; in hasThumb()
465 return getSTI().getFeatureBits()[ARM::FeatureThumb2]; in hasThumb2()
469 return getSTI().getFeatureBits()[ARM::HasV6Ops]; in hasV6Ops()
[all …]

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