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Searched refs:ArgInfo (Results 1 – 25 of 30) sorted by relevance

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/third_party/skia/third_party/externals/angle2/src/libANGLE/renderer/
DCLKernelImpl.cpp21 CLKernelImpl::ArgInfo::ArgInfo() = default;
23 CLKernelImpl::ArgInfo::~ArgInfo() = default;
25 CLKernelImpl::ArgInfo::ArgInfo(ArgInfo &&) = default;
27 CLKernelImpl::ArgInfo &CLKernelImpl::ArgInfo::operator=(ArgInfo &&) = default;
DCLKernelImpl.h42 struct ArgInfo struct
44 ArgInfo();
45 ~ArgInfo();
47 ArgInfo(const ArgInfo &) = delete;
48 ArgInfo &operator=(const ArgInfo &) = delete; argument
50 ArgInfo(ArgInfo &&);
51 ArgInfo &operator=(ArgInfo &&); argument
80 std::vector<ArgInfo> args; argument
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIMachineFunctionInfo.cpp77 ArgInfo.PrivateSegmentBuffer = in SIMachineFunctionInfo()
79 ArgInfo.PrivateSegmentWaveByteOffset = in SIMachineFunctionInfo()
124 ArgInfo.PrivateSegmentWaveByteOffset = in SIMachineFunctionInfo()
189 ArgInfo.PrivateSegmentBuffer = in addPrivateSegmentBuffer()
193 return ArgInfo.PrivateSegmentBuffer.getRegister(); in addPrivateSegmentBuffer()
197 ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addDispatchPtr()
200 return ArgInfo.DispatchPtr.getRegister(); in addDispatchPtr()
204 ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addQueuePtr()
207 return ArgInfo.QueuePtr.getRegister(); in addQueuePtr()
211 ArgInfo.KernargSegmentPtr in addKernargSegmentPtr()
[all …]
DSIMachineFunctionInfo.h283 Optional<SIArgumentInfo> ArgInfo;
312 YamlIO.mapOptional("argumentInfo", MFI.ArgInfo);
341 AMDGPUFunctionArgInfo ArgInfo;
544 ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(getNextSystemSGPR());
546 return ArgInfo.WorkGroupIDX.getRegister();
550 ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(getNextSystemSGPR());
552 return ArgInfo.WorkGroupIDY.getRegister();
556 ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(getNextSystemSGPR());
558 return ArgInfo.WorkGroupIDZ.getRegister();
562 ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(getNextSystemSGPR());
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DAMDGPUTargetMachine.cpp1100 if (YamlMFI.ArgInfo && in parseMachineFunctionInfo()
1101 (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer, in parseMachineFunctionInfo()
1103 MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) || in parseMachineFunctionInfo()
1104 parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr, in parseMachineFunctionInfo()
1105 AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr, in parseMachineFunctionInfo()
1107 parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass, in parseMachineFunctionInfo()
1108 MFI->ArgInfo.QueuePtr, 2, 0) || in parseMachineFunctionInfo()
1109 parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr, in parseMachineFunctionInfo()
1111 MFI->ArgInfo.KernargSegmentPtr, 2, 0) || in parseMachineFunctionInfo()
1112 parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID, in parseMachineFunctionInfo()
[all …]
DAMDGPUCallLowering.h35 void splitToValueTypes(const ArgInfo &OrigArgInfo,
36 SmallVectorImpl<ArgInfo> &SplitArgs,
DAMDGPUArgumentUsageInfo.h174 void setFuncArgInfo(const Function &F, const AMDGPUFunctionArgInfo &ArgInfo) { in setFuncArgInfo() argument
175 ArgInfoMap[&F] = ArgInfo; in setFuncArgInfo()
DAMDGPUCallLowering.cpp68 const CallLowering::ArgInfo &Info, in assignArg()
154 const ArgInfo &OrigArg, SmallVectorImpl<ArgInfo> &SplitArgs, in splitToValueTypes()
275 ArgInfo OrigRetInfo(VRegs, Val->getType()); in lowerReturnVal()
277 SmallVector<ArgInfo, 4> SplitRetInfos; in lowerReturnVal()
606 SmallVector<ArgInfo, 32> SplitArgs; in lowerFormalArguments()
646 ArgInfo OrigArg(VRegs[Idx], Arg.getType()); in lowerFormalArguments()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DCallLowering.h46 struct ArgInfo { struct
56 ArgInfo(ArrayRef<Register> Regs, Type *Ty, argument
68 ArgInfo() : Ty(nullptr), IsFixed(false) {} in ArgInfo() function
80 ArgInfo OrigRet;
83 SmallVector<ArgInfo, 8> OrigArgs;
148 virtual unsigned assignCustomValue(const ArgInfo &Arg, in assignCustomValue()
158 CCValAssign::LocInfo LocInfo, const ArgInfo &Info, in assignArg()
184 void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL,
210 SmallVectorImpl<ArgInfo> &Args,
215 SmallVectorImpl<ArgInfo> &Args,
[all …]
DLegalizerHelper.h255 const CallLowering::ArgInfo &Result,
256 ArrayRef<CallLowering::ArgInfo> Args);
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64CallLowering.h50 SmallVectorImpl<ArgInfo> &InArgs,
51 SmallVectorImpl<ArgInfo> &OutArgs) const;
62 void splitToValueTypes(const ArgInfo &OrigArgInfo,
63 SmallVectorImpl<ArgInfo> &SplitArgs,
68 SmallVectorImpl<ArgInfo> &OutArgs) const;
73 SmallVectorImpl<ArgInfo> &InArgs) const;
77 SmallVectorImpl<ArgInfo> &OutArgs) const;
DAArch64CallLowering.cpp191 const CallLowering::ArgInfo &Info, in assignArg()
220 const ArgInfo &OrigArg, SmallVectorImpl<ArgInfo> &SplitArgs, in splitToValueTypes()
280 SmallVector<ArgInfo, 8> SplitArgs; in lowerReturn()
290 ArgInfo CurArgInfo = ArgInfo{CurVReg, SplitEVTs[i].getTypeForEVT(Ctx)}; in lowerReturn()
424 SmallVector<ArgInfo, 8> SplitArgs; in lowerFormalArguments()
430 ArgInfo OrigArg{VRegs[i], Arg.getType()}; in lowerFormalArguments()
523 SmallVectorImpl<ArgInfo> &InArgs) const { in doCallerAndCalleePassArgsTheSameWay()
563 SmallVectorImpl<ArgInfo> &OutArgs) const { in areCalleeOutgoingArgsTailCallable()
629 ArgInfo &OutInfo = OutArgs[i]; in areCalleeOutgoingArgsTailCallable()
662 SmallVectorImpl<ArgInfo> &InArgs, in isEligibleForTailCallOptimization()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsCallLowering.h34 ArrayRef<CallLowering::ArgInfo> Args);
79 void subTargetRegTypeForCallingConv(const Function &F, ArrayRef<ArgInfo> Args,
85 void splitToValueTypes(const DataLayout &DL, const ArgInfo &OrigArg,
87 SmallVectorImpl<ArgInfo> &SplitArgs,
DMipsCallLowering.cpp56 ArrayRef<CCValAssign> ArgLocs, ArrayRef<CallLowering::ArgInfo> Args) { in handle()
428 SmallVector<ArgInfo, 8> RetInfos; in lowerReturn()
431 ArgInfo ArgRetInfo(VRegs, Val->getType()); in lowerReturn()
470 SmallVector<ArgInfo, 8> ArgInfos; in lowerFormalArguments()
474 ArgInfo AInfo(VRegs[i], Arg.getType()); in lowerFormalArguments()
588 SmallVector<ArgInfo, 8> ArgInfos; in lowerCall()
674 const Function &F, ArrayRef<ArgInfo> Args, in subTargetRegTypeForCallingConv()
704 const DataLayout &DL, const ArgInfo &OrigArg, unsigned OriginalIndex, in splitToValueTypes()
705 SmallVectorImpl<ArgInfo> &SplitArgs, in splitToValueTypes()
716 ArgInfo Info = ArgInfo{OrigArg.Regs[i], SplitEVTs[i].getTypeForEVT(Ctx)}; in splitToValueTypes()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86CallLowering.cpp53 bool X86CallLowering::splitToValueTypes(const ArgInfo &OrigArg, in splitToValueTypes()
54 SmallVectorImpl<ArgInfo> &SplitArgs, in splitToValueTypes()
85 ArgInfo Info = in splitToValueTypes()
86 ArgInfo{MRI.createGenericVirtualRegister(getLLTForType(*PartTy, DL)), in splitToValueTypes()
160 const CallLowering::ArgInfo &Info, ISD::ArgFlagsTy Flags, in assignArg()
207 SmallVector<ArgInfo, 8> SplitArgs; in lowerReturn()
209 ArgInfo CurArgInfo = ArgInfo{VRegs[i], SplitEVTs[i].getTypeForEVT(Ctx)}; in lowerReturn()
341 SmallVector<ArgInfo, 8> SplitArgs; in lowerFormalArguments()
354 ArgInfo OrigArg(VRegs[Idx], Arg.getType()); in lowerFormalArguments()
407 SmallVector<ArgInfo, 8> SplitArgs; in lowerCall()
DX86CallLowering.h44 bool splitToValueTypes(const ArgInfo &OrigArgInfo,
45 SmallVectorImpl<ArgInfo> &SplitArgs,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMCallLowering.cpp140 unsigned assignCustomValue(const CallLowering::ArgInfo &Arg, in assignCustomValue()
174 const CallLowering::ArgInfo &Info, ISD::ArgFlagsTy Flags, in assignArg()
190 void ARMCallLowering::splitToValueTypes(const ArgInfo &OrigArg, in splitToValueTypes()
191 SmallVectorImpl<ArgInfo> &SplitArgs, in splitToValueTypes()
252 ArgInfo OrigRetInfo(VRegs, Val->getType()); in lowerReturnVal()
255 SmallVector<ArgInfo, 4> SplitRetInfos; in lowerReturnVal()
364 unsigned assignCustomValue(const ARMCallLowering::ArgInfo &Arg, in assignCustomValue()
449 SmallVector<ArgInfo, 8> SplitArgInfos; in lowerFormalArguments()
452 ArgInfo OrigArgInfo(VRegs[Idx], Arg.getType()); in lowerFormalArguments()
543 SmallVector<ArgInfo, 8> ArgInfos; in lowerCall()
DARMCallLowering.h51 void splitToValueTypes(const ArgInfo &OrigArg,
52 SmallVectorImpl<ArgInfo> &SplitArgs,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DCallLowering.cpp46 ArgInfo OrigArg{ArgRegs[i], Arg->getType(), ISD::ArgFlagsTy{}, in lowerCall()
58 Info.OrigRet = ArgInfo{ResRegs, CS.getType(), ISD::ArgFlagsTy{}}; in lowerCall()
78 void CallLowering::setArgFlags(CallLowering::ArgInfo &Arg, unsigned OpIdx, in setArgFlags()
121 CallLowering::setArgFlags<Function>(CallLowering::ArgInfo &Arg, unsigned OpIdx,
126 CallLowering::setArgFlags<CallInst>(CallLowering::ArgInfo &Arg, unsigned OpIdx,
172 SmallVectorImpl<ArgInfo> &Args, in handleAssignments()
184 SmallVectorImpl<ArgInfo> &Args, in handleAssignments()
384 SmallVectorImpl<ArgInfo> &Args, in analyzeArgInfo()
402 SmallVectorImpl<ArgInfo> &InArgs, in resultsCompatible()
DLegalizerHelper.cpp361 const CallLowering::ArgInfo &Result, in createLibcall()
362 ArrayRef<CallLowering::ArgInfo> Args) { in createLibcall()
384 SmallVector<CallLowering::ArgInfo, 3> Args; in simpleLibcall()
397 SmallVector<CallLowering::ArgInfo, 3> Args; in createMemLibcall()
436 Info.OrigRet = CallLowering::ArgInfo({0}, Type::getVoidTy(Ctx)); in createMemLibcall()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/IR/
DFunction.cpp832 unsigned ArgInfo = (NextElt == Infos.size() ? 0 : Infos[NextElt++]); in DecodeIITType() local
833 OutputTable.push_back(IITDescriptor::get(IITDescriptor::Argument, ArgInfo)); in DecodeIITType()
837 unsigned ArgInfo = (NextElt == Infos.size() ? 0 : Infos[NextElt++]); in DecodeIITType() local
839 ArgInfo)); in DecodeIITType()
843 unsigned ArgInfo = (NextElt == Infos.size() ? 0 : Infos[NextElt++]); in DecodeIITType() local
845 ArgInfo)); in DecodeIITType()
849 unsigned ArgInfo = (NextElt == Infos.size() ? 0 : Infos[NextElt++]); in DecodeIITType() local
851 ArgInfo)); in DecodeIITType()
855 unsigned ArgInfo = (NextElt == Infos.size() ? 0 : Infos[NextElt++]); in DecodeIITType() local
857 ArgInfo)); in DecodeIITType()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/AsmParser/
DLLParser.h543 struct ArgInfo { struct
548 ArgInfo(LocTy L, Type *ty, AttributeSet Attr, const std::string &N) in ArgInfo() argument
551 bool ParseArgumentList(SmallVectorImpl<ArgInfo> &ArgList, bool &isVarArg);
/third_party/skia/third_party/externals/angle2/src/libANGLE/
DCLKernel.cpp163 const rx::CLKernelImpl::ArgInfo &info = mInfo.args[argIndex]; in getArgInfo()
/third_party/skia/third_party/externals/angle2/src/libANGLE/renderer/cl/
DCLKernelCL.cpp214 ArgInfo &arg = info.args[index]; in createInfo()
/third_party/python/Lib/
Dinspect.py1345 ArgInfo = namedtuple('ArgInfo', 'args varargs keywords locals') variable
1355 return ArgInfo(args, varargs, varkw, frame.f_locals)

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