| /third_party/mesa3d/src/mesa/drivers/dri/i965/ |
| D | brw_misc_state.c | 61 BEGIN_BATCH(1); in upload_pipelined_state_pointers()
66 BEGIN_BATCH(7); in upload_pipelined_state_pointers()
292 BEGIN_BATCH(len); in brw_emit_depth_stencil_hiz()
487 BEGIN_BATCH(2); in brw_emit_select_pipeline()
503 BEGIN_BATCH(9); in brw_emit_select_pipeline()
551 BEGIN_BATCH(1); in brw_emit_select_pipeline()
557 BEGIN_BATCH(1); in brw_emit_select_pipeline()
576 BEGIN_BATCH(7); in brw_emit_select_pipeline()
706 BEGIN_BATCH(3); in brw_upload_invariant_state()
712 BEGIN_BATCH(2); in brw_upload_invariant_state()
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| D | hsw_sol.c | 104 BEGIN_BATCH(9); in tally_prims_written()
127 BEGIN_BATCH(5); in tally_prims_written()
136 BEGIN_BATCH(9); in tally_prims_written()
173 BEGIN_BATCH(1 + 2 * BRW_MAX_XFB_STREAMS); in hsw_begin_transform_feedback()
208 BEGIN_BATCH(3); in hsw_pause_transform_feedback()
235 BEGIN_BATCH(3); in hsw_resume_transform_feedback()
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| D | hsw_queryobj.c | 74 BEGIN_BATCH(1 + ARRAY_SIZE(maths)); in mult_gpr0_by_80()
99 BEGIN_BATCH(1 + ARRAY_SIZE(maths)); in keep_gpr0_lower_n_bits()
130 BEGIN_BATCH(batch_len); in shl_gpr0_by_30_bits()
178 BEGIN_BATCH(1 + ARRAY_SIZE(maths)); in gpr0_to_bool()
234 BEGIN_BATCH(1 + ARRAY_SIZE(maths)); in calc_overflow_for_stream()
317 BEGIN_BATCH(5); in hsw_result_to_gpr0()
394 BEGIN_BATCH(1); in set_predicate()
417 BEGIN_BATCH(dwords * cmd_size); in store_query_result_reg()
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| D | brw_batch.c | 649 BEGIN_BATCH(2); in brw_finish_batch()
937 BEGIN_BATCH(1); in brw_batch_maybe_noop()
1125 BEGIN_BATCH(4 * size); in load_sized_register_mem()
1133 BEGIN_BATCH(3 * size); in load_sized_register_mem()
1173 BEGIN_BATCH(4); in brw_store_register_mem32()
1179 BEGIN_BATCH(3); in brw_store_register_mem32()
1202 BEGIN_BATCH(8); in brw_store_register_mem64()
1211 BEGIN_BATCH(6); in brw_store_register_mem64()
1230 BEGIN_BATCH(3); in brw_load_register_imm32()
1245 BEGIN_BATCH(5); in brw_load_register_imm64()
[all …]
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| D | brw_binding_tables.c | 88 BEGIN_BATCH(2); in brw_upload_binding_table()
251 BEGIN_BATCH(6); in gfx4_upload_binding_table_pointers()
281 BEGIN_BATCH(4); in gfx6_upload_binding_table_pointers()
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| D | gfx7_sol_state.c | 113 BEGIN_BATCH(3); in gfx7_pause_transform_feedback()
140 BEGIN_BATCH(3); in gfx7_resume_transform_feedback()
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| D | brw_state_upload.c | 128 BEGIN_BATCH(2); in brw_upload_gfx11_slice_hashing_state()
145 BEGIN_BATCH(2); in brw_upload_gfx11_slice_hashing_state()
219 BEGIN_BATCH(5); in brw_upload_initial_gpu_state()
227 BEGIN_BATCH(2); in brw_upload_initial_gpu_state()
240 BEGIN_BATCH(3); in brw_upload_initial_gpu_state()
247 BEGIN_BATCH(3); in brw_upload_initial_gpu_state()
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| D | brw_curbe.c | 168 BEGIN_BATCH(2); in brw_upload_cs_urb_state()
306 BEGIN_BATCH(2); in brw_upload_constant_buffer()
336 BEGIN_BATCH(2); in brw_upload_constant_buffer()
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| D | gfx6_sol.c | 418 BEGIN_BATCH(4); in brw_begin_transform_feedback()
430 BEGIN_BATCH(4); in brw_begin_transform_feedback()
500 BEGIN_BATCH(4); in brw_resume_transform_feedback()
512 BEGIN_BATCH(4); in brw_resume_transform_feedback()
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| D | gfx8_multisample_state.c | 36 BEGIN_BATCH(9); in gfx8_emit_3dstate_sample_pattern()
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| D | gfx6_sampler_state.c | 36 BEGIN_BATCH(4); in upload_sampler_state_pointers()
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| D | gfx7_urb.c | 147 BEGIN_BATCH(10); in gfx7_emit_push_constant_state()
257 BEGIN_BATCH(8); in gfx7_upload_urb()
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| D | gfx7_l3_state.c | 146 BEGIN_BATCH(7); in setup_l3_config()
178 BEGIN_BATCH(5); in setup_l3_config()
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| /third_party/mesa3d/src/gallium/drivers/i915/ |
| D | i915_blit.c | 64 if (!BEGIN_BATCH(6)) { in i915_fill_blit()
66 assert(BEGIN_BATCH(6)); in i915_fill_blit()
127 if (!BEGIN_BATCH(8)) { in i915_copy_blit()
129 assert(BEGIN_BATCH(8)); in i915_copy_blit()
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| D | i915_clear.c | 125 if (!BEGIN_BATCH(1 + 2 * (7 + 7))) { in i915_clear_emit()
131 assert(BEGIN_BATCH(1 + 2 * (7 + 7))); in i915_clear_emit()
176 if (!BEGIN_BATCH(1 + 7 + 7)) { in i915_clear_emit()
182 assert(BEGIN_BATCH(1 + 7 + 7)); in i915_clear_emit()
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| D | i915_prim_vbuf.c | 427 if (!BEGIN_BATCH(1 + (nr_indices + 1) / 2)) { in draw_arrays_fallback()
435 if (!BEGIN_BATCH(1 + (nr_indices + 1) / 2)) { in draw_arrays_fallback()
474 if (!BEGIN_BATCH(2)) { in i915_vbuf_render_draw_arrays()
482 if (!BEGIN_BATCH(2)) { in i915_vbuf_render_draw_arrays()
588 if (!BEGIN_BATCH(1 + (nr_indices + 1) / 2)) { in i915_vbuf_render_draw_elements()
596 if (!BEGIN_BATCH(1 + (nr_indices + 1) / 2)) { in i915_vbuf_render_draw_elements()
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| D | i915_prim_emit.c | 135 if (!BEGIN_BATCH(1 + nr * vertex_size / 4)) { in emit_prim()
142 if (!BEGIN_BATCH(1 + nr * vertex_size / 4)) { in emit_prim()
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| D | i915_batch.h | 34 #define BEGIN_BATCH(dwords) (i915_winsys_batchbuffer_check(i915->batch, dwords)) macro
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| /third_party/mesa3d/src/mesa/drivers/dri/radeon/ |
| D | radeon_ioctl.c | 100 BEGIN_BATCH(6); in radeonEmitScissor()
111 BEGIN_BATCH(2); in radeonEmitScissor()
134 BEGIN_BATCH(8); in radeonEmitVbufPrim()
153 BEGIN_BATCH(4); in radeonEmitVbufPrim()
236 BEGIN_BATCH(2+ELTS_BUFSZ(align_min_nr)/4); in radeonAllocEltsOpenEnded()
246 BEGIN_BATCH(ELTS_BUFSZ(align_min_nr)/4); in radeonAllocEltsOpenEnded()
288 BEGIN_BATCH(7); in radeonEmitVertexAOS()
319 BEGIN_BATCH(sz+2+(nr * 2)); in radeonEmitAOS()
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| D | radeon_blit.c | 84 BEGIN_BATCH(8); in emit_vtx_state()
125 BEGIN_BATCH(18); in emit_tx_setup()
200 BEGIN_BATCH(18); in emit_cb_setup()
288 BEGIN_BATCH(15); in emit_draw_packet()
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| D | radeon_state_init.c | 266 BEGIN_BATCH(dwords); in scl_emit()
278 BEGIN_BATCH(dwords); in vec_emit()
290 BEGIN_BATCH(dwords); in lit_emit()
372 BEGIN_BATCH(dwords); in ctx_emit_cs()
405 BEGIN_BATCH(4); in ctx_emit_cs()
444 BEGIN_BATCH(dwords); in cube_emit_cs()
476 BEGIN_BATCH(dwords); in tex_emit_cs()
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| /third_party/mesa3d/src/mesa/drivers/dri/r200/ |
| D | r200_blit.c | 87 BEGIN_BATCH(14); in emit_vtx_state()
154 BEGIN_BATCH(10);
178 BEGIN_BATCH(10);
208 BEGIN_BATCH(34);
281 BEGIN_BATCH(18);
349 BEGIN_BATCH(22);
439 BEGIN_BATCH(14);
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| D | r200_cmdbuf.c | 130 BEGIN_BATCH(3); in r200EmitVbufPrim()
142 BEGIN_BATCH(8+2); in r200FireEB()
214 BEGIN_BATCH(2); in r200EmitMaxVtxIndex()
231 BEGIN_BATCH(7); in r200EmitVertexAOS()
250 BEGIN_BATCH(sz+2+ (nr*2)); in r200EmitAOS()
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| D | radeon_cmdbuf.h | 34 #define BEGIN_BATCH(n) rcommonBeginBatch(b_l_rmesa, n, __FILE__, __func__, __LINE__) macro
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| /third_party/mesa3d/src/mesa/drivers/dri/i915/ |
| D | intel_blit.c | 180 BEGIN_BATCH(8); in emit_copy_blit()
475 BEGIN_BATCH(6); in intelClearWithBlit()
545 BEGIN_BATCH(8 + 3); in intelEmitImmediateColorExpandBlit()
659 BEGIN_BATCH(6); in intel_miptree_set_alpha_to_one()
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