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Searched refs:BaseReg (Results 1 – 25 of 73) sorted by relevance

123

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86FixupLEAs.cpp368 Register BaseReg = Base.getReg(); in optTwoAddrLEA() local
377 if (BaseReg != 0) in optTwoAddrLEA()
378 BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit); in optTwoAddrLEA()
387 if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0 && in optTwoAddrLEA()
388 (DestReg == BaseReg || DestReg == IndexReg)) { in optTwoAddrLEA()
390 if (DestReg != BaseReg) in optTwoAddrLEA()
391 std::swap(BaseReg, IndexReg); in optTwoAddrLEA()
396 .addReg(BaseReg).addReg(IndexReg) in optTwoAddrLEA()
401 .addReg(BaseReg).addReg(IndexReg); in optTwoAddrLEA()
403 } else if (DestReg == BaseReg && IndexReg == 0) { in optTwoAddrLEA()
[all …]
DX86InsertPrefetch.cpp82 Register BaseReg = MI.getOperand(Op + X86::AddrBaseReg).getReg(); in IsMemOpCompatibleWithPrefetch() local
84 return (BaseReg == 0 || in IsMemOpCompatibleWithPrefetch()
85 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) || in IsMemOpCompatibleWithPrefetch()
86 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg)) && in IsMemOpCompatibleWithPrefetch()
DX86AsmPrinter.cpp285 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintLeaMemReference() local
290 bool HasBaseReg = BaseReg.getReg() != 0; in PrintLeaMemReference()
292 BaseReg.getReg() == X86::RIP) in PrintLeaMemReference()
350 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintIntelMemReference() local
357 bool HasBaseReg = BaseReg.getReg() != 0; in PrintIntelMemReference()
359 BaseReg.getReg() == X86::RIP) in PrintIntelMemReference()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIFixupVectorISel.cpp86 unsigned &BaseReg, in findSRegBaseAndIndex() argument
115 BaseReg = DefInst->getOperand(2).getReg(); in findSRegBaseAndIndex()
132 MI = MRI.getUniqueVRegDef(BaseReg); in findSRegBaseAndIndex()
136 BaseReg = MI->getOperand(1).getReg(); in findSRegBaseAndIndex()
137 BaseRC = MRI.getRegClass(BaseReg); in findSRegBaseAndIndex()
141 if (!TRI->isSGPRReg(MRI, BaseReg)) in findSRegBaseAndIndex()
147 MRI.clearKillFlags(BaseReg); in findSRegBaseAndIndex()
175 unsigned BaseReg = 0; in fixupGlobalSaddr() local
178 if (!findSRegBaseAndIndex(Op, BaseReg, IndexReg, MRI, TRI)) in fixupGlobalSaddr()
192 NewGlob->addOperand(MF, MachineOperand::CreateReg(BaseReg, false)); in fixupGlobalSaddr()
DSIRegisterInfo.h90 unsigned BaseReg, int FrameIdx,
93 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
96 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/
DARCRegisterInfo.cpp46 unsigned BaseReg = FrameReg; in ReplaceFrameIndex() local
51 .addReg(BaseReg) in ReplaceFrameIndex()
60 BaseReg = RS->FindUnusedReg(&ARC::GPR32RegClass); in ReplaceFrameIndex()
61 if (!BaseReg) { in ReplaceFrameIndex()
66 BaseReg = RS->scavengeRegister(&ARC::GPR32RegClass, II, SPAdj); in ReplaceFrameIndex()
67 assert(BaseReg && "Register scavenging failed."); in ReplaceFrameIndex()
68 LLVM_DEBUG(dbgs() << "Scavenged register " << printReg(BaseReg, TRI) in ReplaceFrameIndex()
72 RS->setRegUsed(BaseReg); in ReplaceFrameIndex()
76 .addReg(BaseReg, RegState::Define) in ReplaceFrameIndex()
94 .addReg(BaseReg, KillState) in ReplaceFrameIndex()
[all …]
DARCOptAddrMode.cpp90 MachineOperand &Incr, unsigned BaseReg);
94 void fixPastUses(ArrayRef<MachineInstr *> Uses, unsigned BaseReg,
287 Register BaseReg = Ldst->getOperand(BasePos).getReg(); in canJoinInstructions() local
297 if (Add->getOperand(0).getReg() == StReg || BaseReg == StReg) { in canJoinInstructions()
305 for (MachineInstr &MI : MRI->use_nodbg_instructions(BaseReg)) { in canJoinInstructions()
343 MachineOperand &Incr, unsigned BaseReg) { in canFixPastUses() argument
449 Register BaseReg = Ldst.getOperand(BasePos).getReg(); in changeToAddrMode() local
463 Ldst.addOperand(MachineOperand::CreateReg(BaseReg, false)); in changeToAddrMode()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DThumbRegisterInfo.cpp126 const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, in emitThumbRegPlusImmInReg() argument
132 (BaseReg != 0 && !isARMLowRegister(BaseReg)); in emitThumbRegPlusImmInReg()
144 assert(BaseReg == ARM::SP && "Unexpected!"); in emitThumbRegPlusImmInReg()
176 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); in emitThumbRegPlusImmInReg()
178 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); in emitThumbRegPlusImmInReg()
189 unsigned BaseReg, int NumBytes, in emitThumbRegPlusImmediate() argument
220 if (BaseReg == ARM::SP) { in emitThumbRegPlusImmediate()
232 if (BaseReg == ARM::SP) { in emitThumbRegPlusImmediate()
238 } else if (DestReg == BaseReg) { in emitThumbRegPlusImmediate()
241 } else if (isARMLowRegister(BaseReg)) { in emitThumbRegPlusImmediate()
[all …]
DThumb2InstrInfo.cpp233 unsigned BaseReg, int NumBytes, in emitT2RegPlusImmediate() argument
237 if (NumBytes == 0 && DestReg != BaseReg) { in emitT2RegPlusImmediate()
239 .addReg(BaseReg, RegState::Kill) in emitT2RegPlusImmediate()
249 if (DestReg != ARM::SP && DestReg != BaseReg && in emitT2RegPlusImmediate()
271 .addReg(BaseReg) in emitT2RegPlusImmediate()
283 .addReg(BaseReg) in emitT2RegPlusImmediate()
296 if (DestReg == ARM::SP && BaseReg != ARM::SP) { in emitT2RegPlusImmediate()
299 .addReg(BaseReg) in emitT2RegPlusImmediate()
302 BaseReg = ARM::SP; in emitT2RegPlusImmediate()
306 assert((DestReg != ARM::SP || BaseReg == ARM::SP) && in emitT2RegPlusImmediate()
[all …]
DARMBaseRegisterInfo.h169 unsigned BaseReg, int FrameIdx,
171 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
173 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
DARMBaseRegisterInfo.cpp631 unsigned BaseReg, int FrameIdx, in materializeFrameBaseRegister() argument
646 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister()
648 MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg) in materializeFrameBaseRegister()
655 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex() argument
674 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); in resolveFrameIndex()
677 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII, this); in resolveFrameIndex()
683 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, in isFrameOffsetLegal() argument
724 NumBits = (BaseReg == ARM::SP ? 8 : 5); in isFrameOffsetLegal()
DARMLoadStoreOptimizer.cpp1630 bool RegDeadKill, bool RegUndef, unsigned BaseReg, in InsertLDR_STR() argument
1638 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef)); in InsertLDR_STR()
1647 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef)); in InsertLDR_STR()
1665 Register BaseReg = BaseOp.getReg(); in FixInvalidRegPairOp() local
1673 bool Errata602117 = EvenReg == BaseReg && in FixInvalidRegPairOp()
1706 .addReg(BaseReg, getKillRegState(BaseKill)) in FixInvalidRegPairOp()
1714 .addReg(BaseReg, getKillRegState(BaseKill)) in FixInvalidRegPairOp()
1735 if (isLd && TRI->regsOverlap(EvenReg, BaseReg)) { in FixInvalidRegPairOp()
1736 assert(!TRI->regsOverlap(OddReg, BaseReg)); in FixInvalidRegPairOp()
1738 false, BaseReg, false, BaseUndef, Pred, PredReg, TII, MI); in FixInvalidRegPairOp()
[all …]
DThumb2SizeReduction.cpp499 Register BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
500 assert(isARMLowRegister(BaseReg)); in ReduceLoadStore()
506 if (MI->getOperand(i).getReg() == BaseReg) { in ReduceLoadStore()
527 Register BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
528 if (BaseReg != ARM::SP) in ReduceLoadStore()
540 Register BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
541 if (BaseReg == ARM::SP && in ReduceLoadStore()
546 } else if (!isARMLowRegister(BaseReg) || in ReduceLoadStore()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DLocalStackSlotAllocation.cpp269 lookupCandidateBaseReg(unsigned BaseReg, in lookupCandidateBaseReg() argument
278 return TRI->isFrameOffsetLegal(&MI, BaseReg, Offset); in lookupCandidateBaseReg()
343 unsigned BaseReg = 0; in insertFrameReferenceRegisters() local
387 lookupCandidateBaseReg(BaseReg, BaseOffset, FrameSizeAdjust, in insertFrameReferenceRegisters()
389 LLVM_DEBUG(dbgs() << " Reusing base register " << BaseReg << "\n"); in insertFrameReferenceRegisters()
406 BaseReg, BaseOffset, FrameSizeAdjust, in insertFrameReferenceRegisters()
415 BaseReg = Fn.getRegInfo().createVirtualRegister(RC); in insertFrameReferenceRegisters()
417 LLVM_DEBUG(dbgs() << " Materializing base register " << BaseReg in insertFrameReferenceRegisters()
424 TRI->materializeFrameBaseRegister(Entry, BaseReg, FrameIdx, in insertFrameReferenceRegisters()
435 assert(BaseReg != 0 && "Unable to allocate virtual base register!"); in insertFrameReferenceRegisters()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/AsmParser/
DX86AsmParser.cpp345 unsigned BaseReg, IndexReg, TmpReg, Scale; member in __anond0e970780111::X86AsmParser::IntelExprStateMachine
368 : State(IES_INIT), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), in IntelExprStateMachine()
377 unsigned getBaseReg() { return BaseReg; } in getBaseReg()
479 if (!BaseReg) { in onPlus()
480 BaseReg = TmpReg; in onPlus()
534 if (!BaseReg) { in onMinus()
535 BaseReg = TmpReg; in onMinus()
763 if (!BaseReg) { in onRBrac()
764 BaseReg = TmpReg; in onRBrac()
899 CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg,
[all …]
DX86Operand.h62 unsigned BaseReg; member
135 if (Mem.BaseReg) in print()
136 OS << ",BaseReg=" << X86IntelInstPrinter::getRegisterName(Mem.BaseReg); in print()
185 return Mem.BaseReg; in getMemBaseReg()
635 Res->Mem.BaseReg = 0;
650 unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
655 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
663 Res->Mem.BaseReg = BaseReg;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.h99 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
101 void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg,
104 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
DAArch64StorePairSuppress.cpp154 Register BaseReg = BaseOp->getReg(); in runOnMachineFunction() local
155 if (PrevBaseReg == BaseReg) { in runOnMachineFunction()
164 PrevBaseReg = BaseReg; in runOnMachineFunction()
DAArch64FalkorHWPFFix.cpp217 Register BaseReg; member
646 Register BaseReg = MI.getOperand(BaseRegIdx).getReg(); in getLoadInfo() local
647 if (BaseReg == AArch64::SP || BaseReg == AArch64::WSP) in getLoadInfo()
652 LI.BaseReg = BaseReg; in getLoadInfo()
662 unsigned Base = TRI->getEncodingValue(LI.BaseReg); in getTag()
756 NewLdI.BaseReg = ScratchReg; in runOnLoop()
773 .addReg(LdI.BaseReg) in runOnLoop()
786 TII->get(AArch64::ORRXrs), LdI.BaseReg) in runOnLoop()
DAArch64LoadStoreOptimizer.cpp174 unsigned BaseReg, int Offset);
1176 Register BaseReg = getLdStBaseOp(LoadMI).getReg(); in findMatchingStore() local
1203 BaseReg == getLdStBaseOp(MI).getReg() && in findMatchingStore()
1218 if (!ModifiedRegUnits.available(BaseReg)) in findMatchingStore()
1447 Register BaseReg = getLdStBaseOp(FirstMI).getReg(); in findMatchingInsn() local
1513 if (BaseReg == MIBaseReg && ((Offset == MIOffset + OffsetStride) || in findMatchingInsn()
1622 if (!ModifiedRegUnits.available(BaseReg)) in findMatchingInsn()
1703 unsigned BaseReg, int Offset) { in isMatchingUpdateInsn() argument
1719 if (MI.getOperand(0).getReg() != BaseReg || in isMatchingUpdateInsn()
1720 MI.getOperand(1).getReg() != BaseReg) in isMatchingUpdateInsn()
[all …]
DAArch64RegisterInfo.cpp398 unsigned BaseReg, in isFrameOffsetLegal() argument
408 unsigned BaseReg, in materializeFrameBaseRegister() argument
420 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister()
423 BuildMI(*MBB, Ins, DL, MCID, BaseReg) in materializeFrameBaseRegister()
429 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex() argument
443 bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII); in resolveFrameIndex()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/AsmParser/
DLanaiAsmParser.cpp129 unsigned BaseReg; member
171 return Mem.BaseReg; in getMemBaseReg()
614 Op->Mem.BaseReg = 0; in MorphToMemImm()
622 MorphToMemRegReg(unsigned BaseReg, std::unique_ptr<LanaiOperand> Op, in MorphToMemRegReg()
626 Op->Mem.BaseReg = BaseReg; in MorphToMemRegReg()
634 MorphToMemRegImm(unsigned BaseReg, std::unique_ptr<LanaiOperand> Op, in MorphToMemRegImm()
638 Op->Mem.BaseReg = BaseReg; in MorphToMemRegImm()
885 unsigned BaseReg = 0; in parseMemoryOperand() local
942 BaseReg = Op->getReg(); in parseMemoryOperand()
970 if (!BaseReg || Lexer.isNot(AsmToken::RBrac)) { in parseMemoryOperand()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp186 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg); in is16BitMemOperand() local
190 if (STI.hasFeature(X86::Mode16Bit) && BaseReg.getReg() == 0 && Disp.isImm() && in is16BitMemOperand()
193 if ((BaseReg.getReg() != 0 && in is16BitMemOperand()
194 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) || in is16BitMemOperand()
205 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg); in is32BitMemOperand() local
208 if ((BaseReg.getReg() != 0 && in is32BitMemOperand()
209 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || in is32BitMemOperand()
213 if (BaseReg.getReg() == X86::EIP) { in is32BitMemOperand()
227 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg); in is64BitMemOperand() local
230 if ((BaseReg.getReg() != 0 && in is64BitMemOperand()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.h136 unsigned BaseReg, int FrameIdx,
138 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
140 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/MCParser/
DMCTargetAsmParser.h67 StringRef BaseReg; member
73 : NeedBracs(false), Imm(0), BaseReg(StringRef()), IndexReg(StringRef()), in IntelExpr()
78 : NeedBracs(needBracs), Imm(imm), BaseReg(baseReg), IndexReg(indexReg), in IntelExpr()
83 bool hasBaseReg() const { return !BaseReg.empty(); } in hasBaseReg()

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