Searched refs:CTX_PP_CNTL (Results 1 – 10 of 10) sorted by relevance
343 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~(R200_MULTI_PASS_ENABLE | in r200UpdateFSRouting()353 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= shader->numArithInstr[0] == 8 ? in r200UpdateFSRouting()357 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_MULTI_PASS_ENABLE; in r200UpdateFSRouting()358 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= shader->numArithInstr[1] == 8 ? in r200UpdateFSRouting()390 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg; in r200UpdateFSRouting()409 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg; in r200UpdateFSRouting()471 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg; in r200UpdateFSRouting()498 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg; in r200UpdateFSRouting()
907 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~(R200_TEX_BLEND_ENABLE_MASK | R200_MULTI_PASS_ENABLE); in r200UpdateAllTexEnv()908 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= rmesa->state.envneeded << R200_TEX_BLEND_0_ENABLE_SHIFT; in r200UpdateAllTexEnv()951 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~(R200_TEX_0_ENABLE << unit); in disable_tex_obj_state()1426 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << unit; in r200_validate_texture()1524 if ((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & R200_TEX_ENABLE_MASK) == R200_TEX_0_ENABLE && in r200UpdateTextureState()1529 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_1_ENABLE; in r200UpdateTextureState()1535 if ((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & R200_TEX_1_ENABLE) && in r200UpdateTextureState()1550 if (!(rmesa->hw.ctx.cmd[CTX_PP_CNTL] & R200_TEX_1_ENABLE)) in r200UpdateTextureState()
764 uint32_t p = rmesa->hw.ctx.cmd[CTX_PP_CNTL]; in r200UpdateSpecular()813 if ( rmesa->hw.ctx.cmd[CTX_PP_CNTL] != p ) { in r200UpdateSpecular()815 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = p; in r200UpdateSpecular()1665 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_ALPHA_TEST_ENABLE; in r200Enable()1667 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~R200_ALPHA_TEST_ENABLE; in r200Enable()1725 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_FOG_ENABLE; in r200Enable()1728 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~R200_FOG_ENABLE; in r200Enable()1776 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_ANTI_ALIAS_LINE; in r200Enable()1778 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~R200_ANTI_ALIAS_LINE; in r200Enable()1853 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_ANTI_ALIAS_POLY; in r200Enable()[all …]
105 #define CTX_PP_CNTL 9 macro
508 OUT_BATCH(atom->cmd[CTX_PP_CNTL]); in ctx_emit_cs()962 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (R200_ANTI_ALIAS_NONE in r200InitState()
565 uint32_t p = rmesa->hw.ctx.cmd[CTX_PP_CNTL]; in radeonUpdateSpecular()628 if ( rmesa->hw.ctx.cmd[CTX_PP_CNTL] != p ) { in radeonUpdateSpecular()630 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = p; in radeonUpdateSpecular()1446 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= RADEON_ALPHA_TEST_ENABLE; in radeonEnable()1448 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~RADEON_ALPHA_TEST_ENABLE; in radeonEnable()1532 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= RADEON_FOG_ENABLE; in radeonEnable()1535 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~RADEON_FOG_ENABLE; in radeonEnable()1581 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= RADEON_ANTI_ALIAS_LINE; in radeonEnable()1583 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~RADEON_ANTI_ALIAS_LINE; in radeonEnable()1590 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= RADEON_PATTERN_ENABLE; in radeonEnable()[all …]
102 OUT_BATCH(rmesa->hw.ctx.cmd[CTX_PP_CNTL] | RADEON_SCISSOR_ENABLE); in radeonEmitScissor()113 OUT_BATCH(rmesa->hw.ctx.cmd[CTX_PP_CNTL] & ~RADEON_SCISSOR_ENABLE); in radeonEmitScissor()
97 #define CTX_PP_CNTL 9 macro
1006 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= in radeon_validate_texture()1068 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~((RADEON_TEX_ENABLE_MASK) | (RADEON_TEX_BLEND_ENABLE_MASK)); in radeonUpdateTextureState()
389 OUT_BATCH(atom->cmd[CTX_PP_CNTL]); in ctx_emit_cs()704 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (RADEON_SCISSOR_ENABLE | in radeonInitState()