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Searched refs:DAG (Results 1 – 25 of 236) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp51 unsigned AMDGPUTargetLowering::numBitsUnsigned(SDValue Op, SelectionDAG &DAG) { in numBitsUnsigned() argument
53 KnownBits Known = DAG.computeKnownBits(Op); in numBitsUnsigned()
57 unsigned AMDGPUTargetLowering::numBitsSigned(SDValue Op, SelectionDAG &DAG) { in numBitsSigned() argument
62 return VT.getSizeInBits() - DAG.ComputeNumSignBits(Op); in numBitsSigned()
674 const SelectionDAG &DAG, in isLoadBitCastBeneficial() argument
689 return allowsMemoryAccessForAlignment(*DAG.getContext(), DAG.getDataLayout(), in isLoadBitCastBeneficial()
1021 const SDLoc &DL, SelectionDAG &DAG) const { in LowerReturn()
1025 return DAG.getNode(AMDGPUISD::ENDPGM, DL, MVT::Other, Chain); in LowerReturn()
1044 SelectionDAG &DAG, in addTokenForArgument() argument
1057 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(), in addTokenForArgument()
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DR600ISelLowering.cpp475 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { in LowerOperation()
476 MachineFunction &MF = DAG.getMachineFunction(); in LowerOperation()
479 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); in LowerOperation()
480 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); in LowerOperation()
481 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); in LowerOperation()
482 case ISD::SHL_PARTS: return LowerSHLParts(Op, DAG); in LowerOperation()
484 case ISD::SRL_PARTS: return LowerSRXParts(Op, DAG); in LowerOperation()
485 case ISD::UADDO: return LowerUADDSUBO(Op, DAG, ISD::ADD, AMDGPUISD::CARRY); in LowerOperation()
486 case ISD::USUBO: return LowerUADDSUBO(Op, DAG, ISD::SUB, AMDGPUISD::BORROW); in LowerOperation()
488 case ISD::FSIN: return LowerTrig(Op, DAG); in LowerOperation()
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DSIISelLowering.h40 SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL,
42 SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const;
43 SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
48 SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
51 SDValue getPreloadedValue(SelectionDAG &DAG,
57 SelectionDAG &DAG) const override;
58 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op,
61 SelectionDAG &DAG) const;
63 SDValue GLC, SDValue DLC, SelectionDAG &DAG) const;
65 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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DR600ISelLowering.h35 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
39 SelectionDAG &DAG) const override;
44 const SDLoc &DL, SelectionDAG &DAG,
50 const SelectionDAG &DAG) const override;
63 SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT, const SDLoc &DL,
68 SDValue OptimizeSwizzle(SDValue BuildVector, SDValue Swz[], SelectionDAG &DAG,
70 SDValue vectorToVerticalVector(SelectionDAG &DAG, SDValue Vector) const;
72 SDValue lowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
73 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
74 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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DAMDGPUISelLowering.h36 SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
39 static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
40 static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
44 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
45 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
49 SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
50 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
51 SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
52 SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
53 SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonISelLowering.h119 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const;
151 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
153 SelectionDAG &DAG) const override;
155 SelectionDAG &DAG) const override;
159 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
160 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
161 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
162 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
163 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
164 SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
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DHexagonISelLoweringHVX.cpp209 const SDLoc &dl, SelectionDAG &DAG) const { in getInt()
211 IntOps.push_back(DAG.getConstant(IntId, dl, MVT::i32)); in getInt()
214 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, ResTy, IntOps); in getInt()
251 SelectionDAG &DAG) const { in opCastElem()
255 return DAG.getBitcast(CastTy, Vec); in opCastElem()
260 SelectionDAG &DAG) const { in opJoin()
261 return DAG.getNode(ISD::CONCAT_VECTORS, dl, typeJoin(ty(Ops)), in opJoin()
267 SelectionDAG &DAG) const { in opSplit()
271 return DAG.SplitVector(Vec, dl, Tys.first, Tys.second); in opSplit()
288 SelectionDAG &DAG) const { in convertToByteIndex()
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DHexagonISelLowering.cpp156 HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) in LowerINTRINSIC_WO_CHAIN()
168 SelectionDAG &DAG, const SDLoc &dl) { in CreateCopyOfByValArgument() argument
169 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32); in CreateCopyOfByValArgument()
170 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), in CreateCopyOfByValArgument()
197 const SDLoc &dl, SelectionDAG &DAG) const { in LowerReturn()
202 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
203 *DAG.getContext()); in LowerReturn()
218 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
222 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
231 return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, RetOps); in LowerReturn()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZSelectionDAGInfo.cpp25 static SDValue emitMemMem(SelectionDAG &DAG, const SDLoc &DL, unsigned Sequence, in emitMemMem() argument
41 return DAG.getNode(Loop, DL, MVT::Other, Chain, Dst, Src, in emitMemMem()
42 DAG.getConstant(Size, DL, PtrVT), in emitMemMem()
43 DAG.getConstant(Size / 256, DL, PtrVT)); in emitMemMem()
44 return DAG.getNode(Sequence, DL, MVT::Other, Chain, Dst, Src, in emitMemMem()
45 DAG.getConstant(Size, DL, PtrVT)); in emitMemMem()
49 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Src, in EmitTargetCodeForMemcpy() argument
56 return emitMemMem(DAG, DL, SystemZISD::MVC, SystemZISD::MVC_LOOP, in EmitTargetCodeForMemcpy()
64 static SDValue memsetStore(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, in memsetStore() argument
70 return DAG.getStore( in memsetStore()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiISelLowering.cpp176 SelectionDAG &DAG) const { in LowerOperation()
179 return LowerMUL(Op, DAG); in LowerOperation()
181 return LowerBR_CC(Op, DAG); in LowerOperation()
183 return LowerConstantPool(Op, DAG); in LowerOperation()
185 return LowerGlobalAddress(Op, DAG); in LowerOperation()
187 return LowerBlockAddress(Op, DAG); in LowerOperation()
189 return LowerJumpTable(Op, DAG); in LowerOperation()
191 return LowerSELECT_CC(Op, DAG); in LowerOperation()
193 return LowerSETCC(Op, DAG); in LowerOperation()
195 return LowerSHL_PARTS(Op, DAG); in LowerOperation()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp198 LowerOperation(SDValue Op, SelectionDAG &DAG) const { in LowerOperation()
201 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); in LowerOperation()
202 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); in LowerOperation()
203 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); in LowerOperation()
204 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); in LowerOperation()
205 case ISD::BR_JT: return LowerBR_JT(Op, DAG); in LowerOperation()
206 case ISD::LOAD: return LowerLOAD(Op, DAG); in LowerOperation()
207 case ISD::STORE: return LowerSTORE(Op, DAG); in LowerOperation()
208 case ISD::VAARG: return LowerVAARG(Op, DAG); in LowerOperation()
209 case ISD::VASTART: return LowerVASTART(Op, DAG); in LowerOperation()
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DXCoreISelLowering.h108 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
114 SelectionDAG &DAG) const override;
150 const SDLoc &dl, SelectionDAG &DAG,
158 const SDLoc &dl, SelectionDAG &DAG,
160 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
162 SelectionDAG &DAG) const;
166 SelectionDAG &DAG) const;
169 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
170 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
171 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGBuilder.cpp194 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
204 static SDValue getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL, in getCopyFromParts() argument
210 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT, V, in getCopyFromParts()
214 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); in getCopyFromParts()
228 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); in getCopyFromParts()
231 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); in getCopyFromParts()
234 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, in getCopyFromParts()
236 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, in getCopyFromParts()
239 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); in getCopyFromParts()
240 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); in getCopyFromParts()
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DLegalizeIntegerTypes.cpp38 LLVM_DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); in PromoteIntegerResult()
52 N->dump(&DAG); dbgs() << "\n"; in PromoteIntegerResult()
217 return DAG.getNode(ISD::AssertSext, SDLoc(N), in PromoteIntRes_AssertSext()
224 return DAG.getNode(ISD::AssertZext, SDLoc(N), in PromoteIntRes_AssertZext()
229 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); in PromoteIntRes_Atomic0()
230 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N), in PromoteIntRes_Atomic0()
242 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N), in PromoteIntRes_Atomic1()
257 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1)); in PromoteIntRes_AtomicCmpSwap()
264 SDVTList VTs = DAG.getVTList(N->getValueType(0), SVT, MVT::Other); in PromoteIntRes_AtomicCmpSwap()
265 SDValue Res = DAG.getAtomicCmpSwap( in PromoteIntRes_AtomicCmpSwap()
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DLegalizeDAG.cpp88 SelectionDAG &DAG; member in __anon0ffed81a0111::SelectionDAGLegalize
98 return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); in getSetCCResultType()
104 SelectionDAGLegalize(SelectionDAG &DAG, in SelectionDAGLegalize() argument
107 : TM(DAG.getTarget()), TLI(DAG.getTargetLoweringInfo()), DAG(DAG), in SelectionDAGLegalize()
207 LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG); in ReplaceNode()
208 dbgs() << " with: "; New->dump(&DAG)); in ReplaceNode()
213 DAG.ReplaceAllUsesWith(Old, New); in ReplaceNode()
220 LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG); in ReplaceNode()
221 dbgs() << " with: "; New->dump(&DAG)); in ReplaceNode()
223 DAG.ReplaceAllUsesWith(Old, New); in ReplaceNode()
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DLegalizeTypesGeneric.cpp42 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); in ExpandRes_BITCAST()
57 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
58 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
62 auto &DL = DAG.getDataLayout(); in ExpandRes_BITCAST()
68 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
69 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
74 if (TLI.hasBigEndianPartOrdering(OutVT, DAG.getDataLayout())) in ExpandRes_BITCAST()
76 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
77 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
82 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
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DLegalizeVectorTypes.cpp36 LLVM_DEBUG(dbgs() << "Scalarize node result " << ResNo << ": "; N->dump(&DAG); in ScalarizeVectorResult()
44 N->dump(&DAG); in ScalarizeVectorResult()
182 return DAG.getNode(N->getOpcode(), SDLoc(N), in ScalarizeVecRes_BinOp()
190 return DAG.getNode(N->getOpcode(), SDLoc(N), in ScalarizeVecRes_TernaryOp()
198 return DAG.getNode(N->getOpcode(), SDLoc(N), Op0.getValueType(), Op0, Op1, in ScalarizeVecRes_FIX()
224 SDValue Result = DAG.getNode(N->getOpcode(), dl, ValueVTs, Opers); in ScalarizeVecRes_StrictFPOp()
244 DAG.ExtractVectorElements(N->getOperand(0), ElemsLHS); in ScalarizeVecRes_OverflowOp()
245 DAG.ExtractVectorElements(N->getOperand(1), ElemsRHS); in ScalarizeVecRes_OverflowOp()
250 SDVTList ScalarVTs = DAG.getVTList( in ScalarizeVecRes_OverflowOp()
252 SDNode *ScalarNode = DAG.getNode( in ScalarizeVecRes_OverflowOp()
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DTargetLowering.cpp51 bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, in isInTailCallPosition() argument
53 const Function &F = DAG.getMachineFunction().getFunction(); in isInTailCallPosition()
126 TargetLowering::makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, in makeLibCall() argument
132 InChain = DAG.getEntryNode(); in makeLibCall()
141 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext()); in makeLibCall()
155 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), in makeLibCall()
156 getPointerTy(DAG.getDataLayout())); in makeLibCall()
158 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); in makeLibCall()
159 TargetLowering::CallLoweringInfo CLI(DAG); in makeLibCall()
283 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT, in softenSetCCOperands() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp201 const SDLoc &DL, SelectionDAG &DAG) const { in LowerReturn()
203 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); in LowerReturn()
204 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); in LowerReturn()
212 const SDLoc &DL, SelectionDAG &DAG) const { in LowerReturn_32()
213 MachineFunction &MF = DAG.getMachineFunction(); in LowerReturn_32()
219 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn_32()
220 *DAG.getContext()); in LowerReturn_32()
244 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
246 DAG.getConstant(0, DL, getVectorIdxTy(DAG.getDataLayout()))); in LowerReturn_32()
247 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsISelLowering.h321 SelectionDAG &DAG) const override;
324 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
330 SelectionDAG &DAG) const override;
385 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
392 SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, in getAddrLocal() argument
395 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), in getAddrLocal()
396 getTargetNode(N, Ty, DAG, GOTFlag)); in getAddrLocal()
398 DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT, in getAddrLocal()
399 MachinePointerInfo::getGOT(DAG.getMachineFunction())); in getAddrLocal()
401 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, in getAddrLocal()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86SelectionDAGInfo.cpp27 SelectionDAG &DAG, ArrayRef<MCPhysReg> ClobberSet) const { in isBaseRegConflictPossible() argument
33 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); in isBaseRegConflictPossible()
38 DAG.getSubtarget().getRegisterInfo()); in isBaseRegConflictPossible()
47 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Val, in EmitTargetCodeForMemset() argument
52 DAG.getMachineFunction().getSubtarget<X86Subtarget>(); in EmitTargetCodeForMemset()
58 assert(!isBaseRegConflictPossible(DAG, ClobberSet)); in EmitTargetCodeForMemset()
74 ? DAG.getTargetLoweringInfo().getLibcallName(RTLIB::BZERO) in EmitTargetCodeForMemset()
76 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); in EmitTargetCodeForMemset()
77 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout()); in EmitTargetCodeForMemset()
78 Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(*DAG.getContext()); in EmitTargetCodeForMemset()
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DX86ISelLowering.cpp102 static void errorUnsupported(SelectionDAG &DAG, const SDLoc &dl, in errorUnsupported() argument
104 MachineFunction &MF = DAG.getMachineFunction(); in errorUnsupported()
105 DAG.getContext()->diagnose( in errorUnsupported()
2068 SDValue X86TargetLowering::emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, in emitStackGuardXorFP() argument
2070 EVT PtrTy = getPointerTy(DAG.getDataLayout()); in emitStackGuardXorFP()
2072 MachineSDNode *Node = DAG.getMachineNode(XorOp, DL, PtrTy, Val); in emitStackGuardXorFP()
2400 SelectionDAG &DAG) const { in getPICJumpTableRelocBase()
2404 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), in getPICJumpTableRelocBase()
2405 getPointerTy(DAG.getDataLayout())); in getPICJumpTableRelocBase()
2582 const SDLoc &Dl, SelectionDAG &DAG) { in lowerMasksToReg() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DMacroFusion.cpp54 static bool fuseInstructionPair(ScheduleDAGInstrs &DAG, SUnit &FirstSU, in fuseInstructionPair() argument
71 if (!DAG.addEdge(&SecondSU, SDep(&FirstSU, SDep::Cluster))) in fuseInstructionPair()
92 dbgs() << "Macro fuse: "; DAG.dumpNodeName(FirstSU); dbgs() << " - "; in fuseInstructionPair()
93 DAG.dumpNodeName(SecondSU); dbgs() << " / "; in fuseInstructionPair()
94 dbgs() << DAG.TII->getName(FirstSU.getInstr()->getOpcode()) << " - " in fuseInstructionPair()
95 << DAG.TII->getName(SecondSU.getInstr()->getOpcode()) << '\n';); in fuseInstructionPair()
99 if (&SecondSU != &DAG.ExitSU) in fuseInstructionPair()
103 SU == &DAG.ExitSU || SU == &SecondSU || SU->isPred(&SecondSU)) in fuseInstructionPair()
105 LLVM_DEBUG(dbgs() << " Bind "; DAG.dumpNodeName(SecondSU); in fuseInstructionPair()
106 dbgs() << " - "; DAG.dumpNodeName(*SU); dbgs() << '\n';); in fuseInstructionPair()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp1045 New = TLO.DAG.getNode(Op.getOpcode(), DL, VT, Op.getOperand(0), in optimizeLogicalImm()
1046 TLO.DAG.getConstant(NewImm, DL, VT)); in optimizeLogicalImm()
1051 SDValue EncConst = TLO.DAG.getTargetConstant(Enc, DL, VT); in optimizeLogicalImm()
1053 TLO.DAG.getMachineNode(NewOpc, DL, VT, Op.getOperand(0), EncConst), 0); in optimizeLogicalImm()
1105 const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const { in computeKnownBitsForTargetNode() argument
1111 Known = DAG.computeKnownBits(Op->getOperand(0), Depth + 1); in computeKnownBitsForTargetNode()
1112 Known2 = DAG.computeKnownBits(Op->getOperand(1), Depth + 1); in computeKnownBitsForTargetNode()
1696 SelectionDAG &DAG, SDValue Chain, in emitStrictFPComparison() argument
1703 return DAG.getNode(Opcode, dl, {VT, MVT::Other}, {Chain, LHS, RHS}); in emitStrictFPComparison()
1707 const SDLoc &dl, SelectionDAG &DAG) { in emitComparison() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/
DARCISelLowering.cpp38 SDLoc dl, SelectionDAG &DAG,
163 SDValue ARCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { in LowerSELECT_CC()
172 SDValue Cmp = DAG.getNode(ARCISD::CMP, dl, MVT::Glue, LHS, RHS); in LowerSELECT_CC()
173 return DAG.getNode(ARCISD::CMOV, dl, TVal.getValueType(), TVal, FVal, in LowerSELECT_CC()
174 DAG.getConstant(ArcCC, dl, MVT::i32), Cmp); in LowerSELECT_CC()
178 SelectionDAG &DAG) const { in LowerSIGN_EXTEND_INREG()
190 SDValue LS = DAG.getNode(ISD::SHL, dl, MVT::i32, Op0, in LowerSIGN_EXTEND_INREG()
191 DAG.getConstant(32 - Width, dl, MVT::i32)); in LowerSIGN_EXTEND_INREG()
192 SDValue SR = DAG.getNode(ISD::SRA, dl, MVT::i32, LS, in LowerSIGN_EXTEND_INREG()
193 DAG.getConstant(32 - Width, dl, MVT::i32)); in LowerSIGN_EXTEND_INREG()
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