Home
last modified time | relevance | path

Searched refs:DL (Results 1 – 25 of 743) sorted by relevance

12345678910>>...30

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZSelectionDAGInfo.cpp25 static SDValue emitMemMem(SelectionDAG &DAG, const SDLoc &DL, unsigned Sequence, in emitMemMem() argument
41 return DAG.getNode(Loop, DL, MVT::Other, Chain, Dst, Src, in emitMemMem()
42 DAG.getConstant(Size, DL, PtrVT), in emitMemMem()
43 DAG.getConstant(Size / 256, DL, PtrVT)); in emitMemMem()
44 return DAG.getNode(Sequence, DL, MVT::Other, Chain, Dst, Src, in emitMemMem()
45 DAG.getConstant(Size, DL, PtrVT)); in emitMemMem()
49 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Src, in EmitTargetCodeForMemcpy() argument
56 return emitMemMem(DAG, DL, SystemZISD::MVC, SystemZISD::MVC_LOOP, in EmitTargetCodeForMemcpy()
64 static SDValue memsetStore(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, in memsetStore() argument
71 Chain, DL, DAG.getConstant(StoreVal, DL, MVT::getIntegerVT(Size * 8)), in memsetStore()
[all …]
DSystemZISelLowering.cpp669 EVT SystemZTargetLowering::getSetCCResultType(const DataLayout &DL, in getSetCCResultType() argument
936 bool SystemZTargetLowering::isLegalAddressingMode(const DataLayout &DL, in isLegalAddressingMode() argument
1271 static SDValue convertLocVTToValVT(SelectionDAG &DAG, const SDLoc &DL, in convertLocVTToValVT() argument
1277 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
1280 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
1284 Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value); in convertLocVTToValVT()
1290 Value = DAG.getBuildVector(MVT::v2i64, DL, {Value, DAG.getUNDEF(MVT::i64)}); in convertLocVTToValVT()
1291 Value = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Value); in convertLocVTToValVT()
1300 static SDValue convertValVTToLocVT(SelectionDAG &DAG, const SDLoc &DL, in convertValVTToLocVT() argument
1304 return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value); in convertValVTToLocVT()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Utils/
DVNCoercion.cpp16 const DataLayout &DL) { in canCoerceMustAliasedValueToLoad() argument
27 uint64_t StoreSize = DL.getTypeSizeInBits(StoredTy); in canCoerceMustAliasedValueToLoad()
34 if (StoreSize < DL.getTypeSizeInBits(LoadTy)) in canCoerceMustAliasedValueToLoad()
38 if (DL.isNonIntegralPointerType(StoredVal->getType()->getScalarType()) != in canCoerceMustAliasedValueToLoad()
39 DL.isNonIntegralPointerType(LoadTy->getScalarType())) { in canCoerceMustAliasedValueToLoad()
54 const DataLayout &DL) { in coerceAvailableValueToLoadTypeHelper() argument
55 assert(canCoerceMustAliasedValueToLoad(StoredVal, LoadedTy, DL) && in coerceAvailableValueToLoadTypeHelper()
58 if (auto *FoldedStoredVal = ConstantFoldConstant(C, DL)) in coerceAvailableValueToLoadTypeHelper()
64 uint64_t StoredValSize = DL.getTypeSizeInBits(StoredValTy); in coerceAvailableValueToLoadTypeHelper()
65 uint64_t LoadedValSize = DL.getTypeSizeInBits(LoadedTy); in coerceAvailableValueToLoadTypeHelper()
[all …]
/third_party/ffmpeg/tests/ref/fate/
Dfilter-formats37 3 channels (FC+DL+DR)
38 4 channels (FC+LFE+DL+DR)
39 4 channels (FL+FR+DL+DR)
40 5 channels (FL+FR+LFE+DL+DR)
41 5 channels (FL+FR+FC+DL+DR)
42 6 channels (FL+FR+FC+LFE+DL+DR)
43 5 channels (FC+BL+BR+DL+DR)
44 6 channels (FC+LFE+BL+BR+DL+DR)
45 6 channels (FL+FR+BL+BR+DL+DR)
46 7 channels (FL+FR+LFE+BL+BR+DL+DR)
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/
DLoads.cpp30 static MaybeAlign getBaseAlign(const Value *Base, const DataLayout &DL) { in getBaseAlign() argument
31 if (const MaybeAlign PA = Base->getPointerAlignment(DL)) in getBaseAlign()
36 return Align(DL.getABITypeAlignment(Ty)); in getBaseAlign()
40 const DataLayout &DL) { in isAligned() argument
41 if (MaybeAlign BA = getBaseAlign(Base, DL)) { in isAligned()
53 const Value *V, Align Alignment, const APInt &Size, const DataLayout &DL, in isDereferenceableAndAlignedPointer() argument
66 Size, DL, CtxI, DT, Visited); in isDereferenceableAndAlignedPointer()
70 V->getPointerDereferenceableBytes(DL, CheckForNonNull)); in isDereferenceableAndAlignedPointer()
72 if (!CheckForNonNull || isKnownNonZero(V, DL, 0, nullptr, CtxI, DT)) { in isDereferenceableAndAlignedPointer()
78 APInt Offset(DL.getTypeStoreSizeInBits(Ty), 0); in isDereferenceableAndAlignedPointer()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp508 SDLoc DL(Op); in LowerOperation() local
514 DAG.getConstant(0, DL, MVT::i32), // SWZ_X in LowerOperation()
515 DAG.getConstant(1, DL, MVT::i32), // SWZ_Y in LowerOperation()
516 DAG.getConstant(2, DL, MVT::i32), // SWZ_Z in LowerOperation()
517 DAG.getConstant(3, DL, MVT::i32) // SWZ_W in LowerOperation()
519 return DAG.getNode(AMDGPUISD::R600_EXPORT, DL, Op.getValueType(), Args); in LowerOperation()
532 SDLoc DL(Op); in LowerOperation() local
549 DAG.getConstant(TextureOp, DL, MVT::i32), in LowerOperation()
551 DAG.getConstant(0, DL, MVT::i32), in LowerOperation()
552 DAG.getConstant(1, DL, MVT::i32), in LowerOperation()
[all …]
DAMDGPUISelLowering.cpp917 const DataLayout &DL = Fn.getParent()->getDataLayout(); in analyzeFormalArgumentsCompute() local
923 unsigned Align = DL.getABITypeAlignment(BaseArgTy); in analyzeFormalArgumentsCompute()
925 unsigned AllocSize = DL.getTypeAllocSize(BaseArgTy); in analyzeFormalArgumentsCompute()
939 ComputeValueVTs(*this, DL, BaseArgTy, ValueVTs, &Offsets, ArgOffset); in analyzeFormalArgumentsCompute()
1021 const SDLoc &DL, SelectionDAG &DAG) const { in LowerReturn() argument
1025 return DAG.getNode(AMDGPUISD::ENDPGM, DL, MVT::Other, Chain); in LowerReturn()
1095 Fn, Reason + FuncName, CLI.DL.getDebugLoc()); in lowerUnhandledCall()
1192 const DataLayout &DL = DAG.getDataLayout(); in LowerGlobalAddress() local
1211 unsigned Offset = MFI->allocateLDSGlobal(DL, *GV); in LowerGlobalAddress()
1256 SDValue AMDGPUTargetLowering::combineFMinMaxLegacy(const SDLoc &DL, EVT VT, in combineFMinMaxLegacy() argument
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/IR/
DMangler.cpp34 const DataLayout &DL, char Prefix) { in getNameWithPrefixImpl() argument
46 if (DL.doNotMangleLeadingQuestionMark() && Name[0] == '?') in getNameWithPrefixImpl()
50 OS << DL.getPrivateGlobalPrefix(); in getNameWithPrefixImpl()
52 OS << DL.getLinkerPrivateGlobalPrefix(); in getNameWithPrefixImpl()
62 const DataLayout &DL, in getNameWithPrefixImpl() argument
64 char Prefix = DL.getGlobalPrefix(); in getNameWithPrefixImpl()
65 return getNameWithPrefixImpl(OS, GVName, PrefixTy, DL, Prefix); in getNameWithPrefixImpl()
69 const DataLayout &DL) { in getNameWithPrefix() argument
70 return getNameWithPrefixImpl(OS, GVName, DL, Default); in getNameWithPrefix()
74 const Twine &GVName, const DataLayout &DL) { in getNameWithPrefix() argument
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Analysis/
DValueTracking.h55 const DataLayout &DL, unsigned Depth = 0,
63 KnownBits computeKnownBits(const Value *V, const DataLayout &DL,
78 const DataLayout &DL,
89 bool isKnownToBeAPowerOfTwo(const Value *V, const DataLayout &DL,
104 bool isKnownNonZero(const Value *V, const DataLayout &DL, unsigned Depth = 0,
117 bool isKnownNonNegative(const Value *V, const DataLayout &DL,
126 bool isKnownPositive(const Value *V, const DataLayout &DL, unsigned Depth = 0,
134 bool isKnownNegative(const Value *V, const DataLayout &DL, unsigned Depth = 0,
142 bool isKnownNonEqual(const Value *V1, const Value *V2, const DataLayout &DL,
158 const DataLayout &DL,
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsISelLowering.cpp577 SDLoc DL(N); in performDivRemCombine() local
579 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue, in performDivRemCombine()
586 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty, in performDivRemCombine()
595 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, in performDivRemCombine()
654 SDLoc DL(Op); in createFPCmp() local
660 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, in createFPCmp()
661 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32)); in createFPCmp()
666 SDValue False, const SDLoc &DL) { in createCMovFP() argument
671 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, in createCMovFP()
705 const SDLoc DL(N); in performSELECTCombine() local
[all …]
DMipsSEISelDAGToDAG.cpp206 void MipsSEDAGToDAGISel::selectAddE(SDNode *Node, const SDLoc &DL) const { in selectAddE()
234 SDValue CstOne = CurDAG->getTargetConstant(1, DL, MVT::i32); in selectAddE()
236 SDValue OuFlag = CurDAG->getTargetConstant(20, DL, MVT::i32); in selectAddE()
238 SDNode *DSPCtrlField = CurDAG->getMachineNode(Mips::RDDSP, DL, MVT::i32, in selectAddE()
242 Mips::EXT, DL, MVT::i32, SDValue(DSPCtrlField, 0), OuFlag, CstOne); in selectAddE()
245 CurDAG->getTargetConstant(6, DL, MVT::i32), CstOne, in selectAddE()
247 SDNode *DSPCFWithCarry = CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, Ops); in selectAddE()
258 CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, InsOps); in selectAddE()
260 SDNode *WrDSP = CurDAG->getMachineNode(Mips::WRDSP, DL, MVT::Glue, in selectAddE()
737 SDLoc DL(Node); in trySelect() local
[all …]
DMipsSEISelLowering.cpp414 SDLoc DL(Op); in lowerSELECT() local
419 SDValue Tmp = DAG.getNode(MipsISD::MTC1_D64, DL, MVT::f64, Op->getOperand(0)); in lowerSELECT()
420 return DAG.getNode(MipsISD::FSELECT, DL, ResTy, Tmp, Op->getOperand(1), in lowerSELECT()
793 static SDValue genConstMult(SDValue X, APInt C, const SDLoc &DL, EVT VT, in genConstMult() argument
797 return DAG.getConstant(0, DL, VT); in genConstMult()
805 return DAG.getNode(ISD::SHL, DL, VT, X, in genConstMult()
806 DAG.getConstant(C.logBase2(), DL, ShiftTy)); in genConstMult()
817 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG); in genConstMult()
818 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG); in genConstMult()
819 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1); in genConstMult()
[all …]
DMipsBranchExpansion.cpp158 void replaceBranch(MachineBasicBlock &MBB, Iter Br, const DebugLoc &DL,
161 MachineBasicBlock::iterator Pos, DebugLoc DL);
335 const DebugLoc &DL, in replaceBranch() argument
340 MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc); in replaceBranch()
367 DebugLoc DL) { in buildProperJumpMI() argument
387 BuildMI(*MBB, Pos, DL, TII->get(JumpOp)).addReg(ATReg); in buildProperJumpMI()
402 DebugLoc DL = I.Br->getDebugLoc(); in expandToLongBranch() local
456 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
459 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)) in expandToLongBranch()
480 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT) in expandToLongBranch()
[all …]
DMipsISelLowering.h308 DataLayout DL) const override { in getABIAlignmentForCallingConv() argument
309 const Align ABIAlign(DL.getABITypeAlignment(ArgTy)); in getABIAlignmentForCallingConv()
337 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
392 SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, in getAddrLocal() argument
395 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), in getAddrLocal()
398 DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT, in getAddrLocal()
401 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, in getAddrLocal()
403 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo); in getAddrLocal()
411 SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, in getAddrGlobal() argument
414 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), in getAddrGlobal()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
DBPFISelDAGToDAG.cpp84 bool fillGenericConstant(const DataLayout &DL, const Constant *CV,
86 bool fillConstantDataArray(const DataLayout &DL, const ConstantDataArray *CDA,
88 bool fillConstantArray(const DataLayout &DL, const ConstantArray *CA,
90 bool fillConstantStruct(const DataLayout &DL, const ConstantStruct *CS,
102 SDLoc DL(Addr); in SelectAddr() local
105 Offset = CurDAG->getTargetConstant(0, DL, MVT::i64); in SelectAddr()
125 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), DL, MVT::i64); in SelectAddr()
131 Offset = CurDAG->getTargetConstant(0, DL, MVT::i64); in SelectAddr()
138 SDLoc DL(Addr); in SelectFIAddr() local
153 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), DL, MVT::i64); in SelectFIAddr()
[all …]
DBPFISelLowering.cpp39 static void fail(const SDLoc &DL, SelectionDAG &DAG, const Twine &Msg) { in fail() argument
42 DiagnosticInfoUnsupported(MF.getFunction(), Msg, DL.getDebugLoc())); in fail()
45 static void fail(const SDLoc &DL, SelectionDAG &DAG, const char *Msg, in fail() argument
54 DiagnosticInfoUnsupported(MF.getFunction(), Str, DL.getDebugLoc())); in fail()
208 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerFormalArguments() argument
242 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerFormalArguments()
247 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
250 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
254 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue); in LowerFormalArguments()
261 fail(DL, DAG, "defined with too many args"); in LowerFormalArguments()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp344 static MachineBasicBlock *LowerFPToInt(MachineInstr &MI, DebugLoc DL, in LowerFPToInt() argument
401 BuildMI(BB, DL, TII.get(Abs), Tmp0).addReg(InReg); in LowerFPToInt()
403 BuildMI(BB, DL, TII.get(FConst), Tmp1) in LowerFPToInt()
405 BuildMI(BB, DL, TII.get(LT), CmpReg).addReg(Tmp0).addReg(Tmp1); in LowerFPToInt()
413 BuildMI(BB, DL, TII.get(FConst), Tmp1) in LowerFPToInt()
415 BuildMI(BB, DL, TII.get(GE), SecondCmpReg).addReg(Tmp0).addReg(Tmp1); in LowerFPToInt()
416 BuildMI(BB, DL, TII.get(And), AndReg).addReg(CmpReg).addReg(SecondCmpReg); in LowerFPToInt()
420 BuildMI(BB, DL, TII.get(Eqz), EqzReg).addReg(CmpReg); in LowerFPToInt()
424 BuildMI(BB, DL, TII.get(WebAssembly::BR_IF)).addMBB(TrueMBB).addReg(EqzReg); in LowerFPToInt()
425 BuildMI(FalseMBB, DL, TII.get(LoweredOpcode), FalseReg).addReg(InReg); in LowerFPToInt()
[all …]
DWebAssemblySelectionDAGInfo.cpp22 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Src, in EmitTargetCodeForMemcpy() argument
30 SDValue MemIdx = DAG.getConstant(0, DL, MVT::i32); in EmitTargetCodeForMemcpy()
31 return DAG.getNode(WebAssemblyISD::MEMORY_COPY, DL, MVT::Other, in EmitTargetCodeForMemcpy()
33 DAG.getZExtOrTrunc(Size, DL, MVT::i32)}); in EmitTargetCodeForMemcpy()
37 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Op1, SDValue Op2, in EmitTargetCodeForMemmove() argument
40 return EmitTargetCodeForMemcpy(DAG, DL, Chain, Op1, Op2, Op3, Align, in EmitTargetCodeForMemmove()
46 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Val, in EmitTargetCodeForMemset() argument
54 SDValue MemIdx = DAG.getConstant(0, DL, MVT::i32); in EmitTargetCodeForMemset()
56 return DAG.getNode(WebAssemblyISD::MEMORY_FILL, DL, MVT::Other, Chain, MemIdx, in EmitTargetCodeForMemset()
57 Dst, DAG.getAnyExtOrTrunc(Val, DL, MVT::i32), in EmitTargetCodeForMemset()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Transforms/Utils/
DVNCoercion.h38 const DataLayout &DL);
47 IRBuilder<> &IRB, const DataLayout &DL);
55 StoreInst *DepSI, const DataLayout &DL);
63 const DataLayout &DL);
71 MemIntrinsic *DepMI, const DataLayout &DL);
77 Instruction *InsertPt, const DataLayout &DL);
81 Type *LoadTy, const DataLayout &DL);
88 Instruction *InsertPt, const DataLayout &DL);
92 Type *LoadTy, const DataLayout &DL);
100 const DataLayout &DL);
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiISelLowering.cpp398 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerFormalArguments() argument
403 return LowerCCCArguments(Chain, CallConv, IsVarArg, Ins, DL, DAG, InVals); in LowerFormalArguments()
412 SDLoc &DL = CLI.DL; in LowerCall() local
429 OutVals, Ins, DL, DAG, InVals); in LowerCall()
439 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerCCCArguments() argument
465 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerCCCArguments()
471 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerCCCArguments()
474 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerCCCArguments()
478 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue); in LowerCCCArguments()
505 VA.getLocVT(), DL, Chain, FIN, in LowerCCCArguments()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVISelLowering.cpp232 EVT RISCVTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &, in getSetCCResultType() argument
235 return getPointerTy(DL); in getSetCCResultType()
267 bool RISCVTargetLowering::isLegalAddressingMode(const DataLayout &DL, in isLegalAddressingMode() argument
413 SDLoc DL(Op); in LowerOperation() local
417 SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0); in LowerOperation()
418 SDValue FPConv = DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, MVT::f32, NewOp0); in LowerOperation()
424 static SDValue getTargetNode(GlobalAddressSDNode *N, SDLoc DL, EVT Ty, in getTargetNode() argument
426 return DAG.getTargetGlobalAddress(N->getGlobal(), DL, Ty, 0, Flags); in getTargetNode()
429 static SDValue getTargetNode(BlockAddressSDNode *N, SDLoc DL, EVT Ty, in getTargetNode() argument
435 static SDValue getTargetNode(ConstantPoolSDNode *N, SDLoc DL, EVT Ty, in getTargetNode() argument
[all …]
DRISCVExpandPseudoInsts.cpp234 DebugLoc DL, MachineBasicBlock *ThisMBB, in doAtomicBinOpExpansion() argument
250 BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg) in doAtomicBinOpExpansion()
256 BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg) in doAtomicBinOpExpansion()
259 BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg) in doAtomicBinOpExpansion()
264 BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg) in doAtomicBinOpExpansion()
267 BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)) in doAtomicBinOpExpansion()
273 static void insertMaskedMerge(const RISCVInstrInfo *TII, DebugLoc DL, in insertMaskedMerge() argument
284 BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg) in insertMaskedMerge()
287 BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg) in insertMaskedMerge()
290 BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg) in insertMaskedMerge()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86FrameLowering.cpp251 const DebugLoc &DL, in emitSPUpdate() argument
275 BuildMI(MBB, MBBI, DL, TII.get(MovRIOpc), Reg) in emitSPUpdate()
278 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AddSubRROpc), StackPtr) in emitSPUpdate()
292 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r)) in emitSPUpdate()
301 BuildMI(MBB, MBBI, DL, TII.get(MovRIOpc), Rax) in emitSPUpdate()
304 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(X86::ADD64rr), Rax) in emitSPUpdate()
310 BuildMI(MBB, MBBI, DL, TII.get(X86::XCHG64rm), Rax).addReg(Rax), in emitSPUpdate()
313 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), StackPtr), in emitSPUpdate()
331 BuildMI(MBB, MBBI, DL, TII.get(Opc)) in emitSPUpdate()
339 BuildStackAdjustment(MBB, MBBI, DL, isSub ? -ThisVal : ThisVal, InEpilogue) in emitSPUpdate()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/
DSROA.cpp235 AllocaSlices(const DataLayout &DL, AllocaInst &AI);
664 SliceBuilder(const DataLayout &DL, AllocaInst &AI, AllocaSlices &AS) in SliceBuilder() argument
665 : PtrUseVisitor<SliceBuilder>(DL), in SliceBuilder()
666 AllocSize(DL.getTypeAllocSize(AI.getAllocatedType())), AS(AS) {} in SliceBuilder()
737 const DataLayout &DL = GEPI.getModule()->getDataLayout(); in visitGetElementPtrInst() local
748 const StructLayout *SL = DL.getStructLayout(STy); in visitGetElementPtrInst()
756 DL.getTypeAllocSize(GTI.getIndexedType())); in visitGetElementPtrInst()
788 LI.getPointerAddressSpace() != DL.getAllocaAddrSpace()) in visitLoadInst()
791 uint64_t Size = DL.getTypeStoreSize(LI.getType()); in visitLoadInst()
803 SI.getPointerAddressSpace() != DL.getAllocaAddrSpace()) in visitStoreInst()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/ObjCARC/
DProvenanceAnalysis.cpp43 const DataLayout &DL = A->getModule()->getDataLayout(); in relatedSelect() local
48 return related(A->getTrueValue(), SB->getTrueValue(), DL) || in relatedSelect()
49 related(A->getFalseValue(), SB->getFalseValue(), DL); in relatedSelect()
52 return related(A->getTrueValue(), B, DL) || in relatedSelect()
53 related(A->getFalseValue(), B, DL); in relatedSelect()
58 const DataLayout &DL = A->getModule()->getDataLayout(); in relatedPHI() local
66 PNB->getIncomingValueForBlock(A->getIncomingBlock(i)), DL)) in relatedPHI()
74 if (UniqueSrc.insert(PV1).second && related(PV1, B, DL)) in relatedPHI()
116 const DataLayout &DL) { in relatedCheck() argument
164 const DataLayout &DL) { in related() argument
[all …]

12345678910>>...30