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Searched refs:DR1 (Results 1 – 13 of 13) sorted by relevance

/third_party/libdrm/include/drm/
Di915_drm.h413 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ member
425 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ member
893 __u32 DR1; member
996 __u32 DR1; member
/third_party/mesa3d/include/drm-uapi/
Di915_drm.h481 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ member
493 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ member
1093 __u32 DR1; member
1228 __u32 DR1; member
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h346 ENTRY(DR1) \
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/DebugInfo/CodeView/
DCodeViewRegisters.def99 CV_REGISTER(DR1, 91)
/third_party/libdrm/intel/
Dintel_bufmgr_fake.c1470 batch.DR1 = 0; in drm_intel_fake_bo_exec()
Dintel_bufmgr_gem.c2331 execbuf.DR1 = 0; in drm_intel_gem_bo_exec()
2421 execbuf.DR1 = 0; in do_exec2()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86RegisterInfo.td325 def DR1 : X86Reg<"dr1", 1>;
/third_party/mesa3d/src/intel/vulkan/
Danv_batch_chain.c1816 .DR1 = 0, in setup_execbuf_for_cmd_buffers()
/third_party/mesa3d/src/mesa/x86/
Dassyntax.h130 #define DR1 dr1 macro
192 #define DR1 %db1 macro
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/AsmParser/
DX86AsmParser.cpp1224 case '1': RegNo = X86::DR1; break; in ParseRegister()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenRegisterInfo.inc108 DR1 = 88,
1208 { X86::DR1 },
1626 …X86::DR0, X86::DR1, X86::DR2, X86::DR3, X86::DR4, X86::DR5, X86::DR6, X86::DR7, X86::DR8, X86::DR9…
DX86GenAsmMatcher.inc7326 case X86::DR1: OpKind = MCK_DEBUG_REG; break;
/third_party/chromium/patch/
D0001-cve.patch70874 zPG`V1a1BBw?+6f&+DR1(FYj(T9oE1agj3$*)QtBywV;->4&ALontKx7>C}XGI<=tI