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Searched refs:DSCSR (Results 1 – 7 of 7) sorted by relevance

/third_party/cmsis/CMSIS/Core/Include/
Dcore_cm23.h1074 …__IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status… member
1175 …__IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status… member
Dcore_armv8mbl.h999 …__IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status… member
1100 …__IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status… member
Dcore_armv8mml.h1741 …__IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status… member
1875 …__IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status… member
Dcore_cm35p.h1816 …__IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status… member
1950 …__IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status… member
Dcore_cm33.h1816 …__IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status… member
1950 …__IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status… member
Dcore_cm55.h2664 …__IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status… member
2835 …__IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status… member
Dcore_armv81mml.h2629 …__IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status… member
2800 …__IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status… member