Home
last modified time | relevance | path

Searched refs:DestReg (Results 1 – 25 of 103) sorted by relevance

12345

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DThumbRegisterInfo.cpp63 const DebugLoc &dl, unsigned DestReg, in emitThumb1LoadConstPool() argument
76 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb1LoadConstPool()
83 const DebugLoc &dl, unsigned DestReg, in emitThumb2LoadConstPool() argument
95 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb2LoadConstPool()
105 const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, in emitLoadConstPool() argument
111 (isARMLowRegister(DestReg) || Register::isVirtualRegister(DestReg)) && in emitLoadConstPool()
113 return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
116 return emitThumb2LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
126 const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, in emitThumbRegPlusImmInReg() argument
131 bool isHigh = !isARMLowRegister(DestReg) || in emitThumbRegPlusImmInReg()
[all …]
DThumb1InstrInfo.cpp40 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
46 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && in copyPhysReg()
50 || !ARM::tGPRRegClass.contains(DestReg)) in copyPhysReg()
51 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
61 BuildMI(MBB, I, DL, get(ARM::tMOVSr), DestReg) in copyPhysReg()
73 .addReg(DestReg, getDefRegState(true)); in copyPhysReg()
107 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
112 (Register::isPhysicalRegister(DestReg) && isARMLowRegister(DestReg))) && in loadRegFromStackSlot()
116 (Register::isPhysicalRegister(DestReg) && isARMLowRegister(DestReg))) { in loadRegFromStackSlot()
125 BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg) in loadRegFromStackSlot()
DThumb2InstrInfo.cpp123 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
126 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
127 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc); in copyPhysReg()
129 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
179 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
191 BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg) in loadRegFromStackSlot()
203 if (Register::isVirtualRegister(DestReg)) { in loadRegFromStackSlot()
205 MRI->constrainRegClass(DestReg, &ARM::GPRPairnospRegClass); in loadRegFromStackSlot()
209 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
210 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
[all …]
DARMBaseInstrInfo.cpp770 unsigned DestReg, bool KillSrc, in copyFromCPSR() argument
777 BuildMI(MBB, I, I->getDebugLoc(), get(Opc), DestReg); in copyFromCPSR()
814 unsigned DestReg) { in addUnpredicatedMveVpredROp() argument
816 MIB.addReg(DestReg, RegState::Undef); in addUnpredicatedMveVpredROp()
832 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
834 bool GPRDest = ARM::GPRRegClass.contains(DestReg); in copyPhysReg()
838 BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) in copyPhysReg()
845 bool SPRDest = ARM::SPRRegClass.contains(DestReg); in copyPhysReg()
855 else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && Subtarget.hasFP64()) in copyPhysReg()
857 else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZPostRewrite.cpp89 Register DestReg = MBBI->getOperand(0).getReg(); in selectLOCRMux() local
91 bool DestIsHigh = SystemZ::isHighReg(DestReg); in selectLOCRMux()
110 Register DestReg = MBBI->getOperand(0).getReg(); in selectSELRMux() local
113 bool DestIsHigh = SystemZ::isHighReg(DestReg); in selectSELRMux()
120 if (DestReg != Src1Reg && DestReg != Src2Reg) { in selectSELRMux()
123 TII->get(SystemZ::COPY), DestReg) in selectSELRMux()
125 MBBI->getOperand(1).setReg(DestReg); in selectSELRMux()
126 Src1Reg = DestReg; in selectSELRMux()
130 TII->get(SystemZ::COPY), DestReg) in selectSELRMux()
132 MBBI->getOperand(2).setReg(DestReg); in selectSELRMux()
[all …]
DSystemZInstrInfo.cpp154 Register DestReg = MI.getOperand(0).getReg(); in expandRIEPseudo() local
156 bool DestIsHigh = SystemZ::isHighReg(DestReg); in expandRIEPseudo()
161 if (DestReg != SrcReg) { in expandRIEPseudo()
162 emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(), DestReg, SrcReg, in expandRIEPseudo()
165 MI.getOperand(1).setReg(DestReg); in expandRIEPseudo()
248 const DebugLoc &DL, unsigned DestReg, in emitGRX32Move() argument
253 bool DestIsHigh = SystemZ::isHighReg(DestReg); in emitGRX32Move()
262 return BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg) in emitGRX32Move()
266 return BuildMI(MBB, MBBI, DL, get(Opcode), DestReg) in emitGRX32Move()
267 .addReg(DestReg, RegState::Undef) in emitGRX32Move()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86FixupLEAs.cpp367 Register DestReg = MI.getOperand(0).getReg(); in optTwoAddrLEA() local
372 if (UseLEAForSP && (DestReg == X86::ESP || DestReg == X86::RSP)) in optTwoAddrLEA()
388 (DestReg == BaseReg || DestReg == IndexReg)) { in optTwoAddrLEA()
390 if (DestReg != BaseReg) in optTwoAddrLEA()
395 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
400 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
403 } else if (DestReg == BaseReg && IndexReg == 0) { in optTwoAddrLEA()
416 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
419 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
426 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcInstrInfo.cpp307 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
321 if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
322 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0) in copyPhysReg()
324 else if (SP::IntPairRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
329 } else if (SP::FPRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
330 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) in copyPhysReg()
332 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
334 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg) in copyPhysReg()
342 } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
345 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg) in copyPhysReg()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVExpandPseudoInsts.cpp238 Register DestReg = MI.getOperand(0).getReg(); in doAtomicBinOpExpansion() local
250 BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg) in doAtomicBinOpExpansion()
257 .addReg(DestReg) in doAtomicBinOpExpansion()
274 MachineBasicBlock *MBB, Register DestReg, in insertMaskedMerge() argument
290 BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg) in insertMaskedMerge()
300 Register DestReg = MI.getOperand(0).getReg(); in doMaskedAtomicBinOpExpansion() local
316 BuildMI(LoopMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg) in doMaskedAtomicBinOpExpansion()
328 .addReg(DestReg) in doMaskedAtomicBinOpExpansion()
333 .addReg(DestReg) in doMaskedAtomicBinOpExpansion()
338 .addReg(DestReg) in doMaskedAtomicBinOpExpansion()
[all …]
DRISCVMergeBaseOffset.cpp181 Register DestReg = LoADDI.getOperand(0).getReg(); in detectAndFoldOffset() local
182 assert(MRI->hasOneUse(DestReg) && "expected one use for LoADDI"); in detectAndFoldOffset()
184 MachineInstr &Tail = *MRI->use_begin(DestReg)->getParent(); in detectAndFoldOffset()
207 if (!matchLargeOffset(Tail, DestReg, Offset)) in detectAndFoldOffset()
236 if (DestReg != BaseAddrReg) in detectAndFoldOffset()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsFastISel.cpp180 bool emitCmp(unsigned DestReg, const CmpInst *CI);
188 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
191 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
193 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
195 unsigned DestReg);
197 unsigned DestReg);
395 unsigned DestReg = createResultReg(RC); in materializeFP() local
397 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
398 return DestReg; in materializeFP()
401 unsigned DestReg = createResultReg(RC); in materializeFP() local
[all …]
DMipsSEInstrInfo.cpp85 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
90 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. in copyPhysReg()
111 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4) in copyPhysReg()
119 if (Mips::CCRRegClass.contains(DestReg)) in copyPhysReg()
121 else if (Mips::FGR32RegClass.contains(DestReg)) in copyPhysReg()
123 else if (Mips::HI32RegClass.contains(DestReg)) in copyPhysReg()
124 Opc = Mips::MTHI, DestReg = 0; in copyPhysReg()
125 else if (Mips::LO32RegClass.contains(DestReg)) in copyPhysReg()
126 Opc = Mips::MTLO, DestReg = 0; in copyPhysReg()
127 else if (Mips::HI32DSPRegClass.contains(DestReg)) in copyPhysReg()
[all …]
DMips16InstrInfo.cpp71 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
75 if (Mips::CPU16RegsRegClass.contains(DestReg) && in copyPhysReg()
78 else if (Mips::GPR32RegClass.contains(DestReg) && in copyPhysReg()
82 (Mips::CPU16RegsRegClass.contains(DestReg))) in copyPhysReg()
85 (Mips::CPU16RegsRegClass.contains(DestReg))) in copyPhysReg()
92 if (DestReg) in copyPhysReg()
93 MIB.addReg(DestReg, RegState::Define); in copyPhysReg()
126 unsigned DestReg, int FI, in loadRegFromStack() argument
138 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset) in loadRegFromStack()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600MachineScheduler.cpp273 Register DestReg = MI->getOperand(0).getReg(); in getAluKind() local
274 if (regBelongsToClass(DestReg, &R600::R600_TReg32_XRegClass) || in getAluKind()
275 regBelongsToClass(DestReg, &R600::R600_AddrRegClass)) in getAluKind()
277 if (regBelongsToClass(DestReg, &R600::R600_TReg32_YRegClass)) in getAluKind()
279 if (regBelongsToClass(DestReg, &R600::R600_TReg32_ZRegClass)) in getAluKind()
281 if (regBelongsToClass(DestReg, &R600::R600_TReg32_WRegClass)) in getAluKind()
283 if (regBelongsToClass(DestReg, &R600::R600_Reg128RegClass)) in getAluKind()
360 Register DestReg = MI->getOperand(DstIndex).getReg(); in AssignSlot() local
367 MO.getReg() == DestReg) in AssignSlot()
373 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_XRegClass); in AssignSlot()
[all …]
DAMDGPUMachineCFGStructurizer.cpp62 unsigned DestReg;
77 PHIInfoElementT *findPHIInfoElement(unsigned DestReg);
84 void addDest(unsigned DestReg, const DebugLoc &DL);
86 void deleteDef(unsigned DestReg);
87 void addSource(unsigned DestReg, unsigned SourceReg,
89 void removeSource(unsigned DestReg, unsigned SourceReg,
92 unsigned &DestReg);
94 unsigned getNumSources(unsigned DestReg);
131 return Info->DestReg; in phiInfoElementGetDest()
136 Info->DestReg = NewDef; in phiInfoElementSetDef()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonSplitConst32AndConst64.cpp79 Register DestReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
82 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestReg) in runOnMachineFunction()
86 Register DestReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
89 Register DestLo = TRI->getSubReg(DestReg, Hexagon::isub_lo); in runOnMachineFunction()
90 Register DestHi = TRI->getSubReg(DestReg, Hexagon::isub_hi); in runOnMachineFunction()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
DBPFInstrInfo.cpp33 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
35 if (BPF::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
36 BuildMI(MBB, I, DL, get(BPF::MOV_rr), DestReg) in copyPhysReg()
38 else if (BPF::GPR32RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
39 BuildMI(MBB, I, DL, get(BPF::MOV_rr_32), DestReg) in copyPhysReg()
149 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
157 BuildMI(MBB, I, DL, get(BPF::LDD), DestReg).addFrameIndex(FI).addImm(0); in loadRegFromStackSlot()
159 BuildMI(MBB, I, DL, get(BPF::LDW32), DestReg).addFrameIndex(FI).addImm(0); in loadRegFromStackSlot()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64AsmPrinter.cpp828 Register DestReg = MI.getOperand(0).getReg(); in LowerJumpTableDestSmall() local
842 .addReg(DestReg) in LowerJumpTableDestSmall()
858 .addReg(DestReg) in LowerJumpTableDestSmall()
859 .addReg(DestReg) in LowerJumpTableDestSmall()
940 Register DestReg = MI.getOperand(0).getReg(); in EmitFMov0() local
943 if (AArch64::H0 <= DestReg && DestReg <= AArch64::H31) in EmitFMov0()
944 DestReg = AArch64::Q0 + (DestReg - AArch64::H0); in EmitFMov0()
945 else if (AArch64::S0 <= DestReg && DestReg <= AArch64::S31) in EmitFMov0()
946 DestReg = AArch64::Q0 + (DestReg - AArch64::S0); in EmitFMov0()
948 assert(AArch64::D0 <= DestReg && DestReg <= AArch64::D31); in EmitFMov0()
[all …]
DAArch64A57FPLoadBalancing.cpp614 Register DestReg = MI->getOperand(0).getReg(); in scanInstruction() local
617 << printReg(DestReg, TRI) << " at " << *MI); in scanInstruction()
619 auto G = std::make_unique<Chain>(MI, Idx, getColor(DestReg)); in scanInstruction()
620 ActiveChains[DestReg] = G.get(); in scanInstruction()
627 Register DestReg = MI->getOperand(0).getReg(); in scanInstruction() local
632 if (DestReg != AccumReg) in scanInstruction()
647 ActiveChains[AccumReg]->add(MI, Idx, getColor(DestReg)); in scanInstruction()
649 if (DestReg != AccumReg) { in scanInstruction()
650 ActiveChains[DestReg] = ActiveChains[AccumReg]; in scanInstruction()
663 << printReg(DestReg, TRI) << "\n"); in scanInstruction()
[all …]
DAArch64InstrInfo.cpp2442 static bool forwardCopyWillClobberTuple(unsigned DestReg, unsigned SrcReg, in forwardCopyWillClobberTuple() argument
2446 return ((DestReg - SrcReg) & 0x1f) < NumRegs; in forwardCopyWillClobberTuple()
2451 const DebugLoc &DL, MCRegister DestReg, in copyPhysRegTuple() argument
2457 uint16_t DestEncoding = TRI->getEncodingValue(DestReg); in copyPhysRegTuple()
2470 AddSubReg(MIB, DestReg, Indices[SubReg], RegState::Define, TRI); in copyPhysRegTuple()
2478 DebugLoc DL, unsigned DestReg, in copyGPRRegTuple() argument
2486 uint16_t DestEncoding = TRI->getEncodingValue(DestReg); in copyGPRRegTuple()
2494 AddSubReg(MIB, DestReg, Indices[SubReg], RegState::Define, TRI); in copyGPRRegTuple()
2503 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
2505 if (AArch64::GPR32spRegClass.contains(DestReg) && in copyPhysReg()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DMachineInstrBuilder.h324 const MCInstrDesc &MCID, Register DestReg) { in BuildMI() argument
326 .addReg(DestReg, RegState::Define); in BuildMI()
335 Register DestReg) { in BuildMI() argument
339 return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define); in BuildMI()
351 Register DestReg) { in BuildMI() argument
355 return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define); in BuildMI()
360 Register DestReg) { in BuildMI() argument
364 return BuildMI(BB, MachineBasicBlock::instr_iterator(I), DL, MCID, DestReg); in BuildMI()
365 return BuildMI(BB, MachineBasicBlock::iterator(I), DL, MCID, DestReg); in BuildMI()
370 Register DestReg) { in BuildMI() argument
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/
DMSP430InstrInfo.cpp65 unsigned DestReg, int FrameIdx, in loadRegFromStackSlot() argument
80 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx) in loadRegFromStackSlot()
84 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx) in loadRegFromStackSlot()
92 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
95 if (MSP430::GR16RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
97 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
102 BuildMI(MBB, I, DL, get(Opc), DestReg) in copyPhysReg()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRInstrInfo.cpp43 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
50 if (AVR::DREGSRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
52 BuildMI(MBB, MI, DL, get(AVR::MOVWRdRr), DestReg) in copyPhysReg()
57 TRI.splitReg(DestReg, DestLo, DestHi); in copyPhysReg()
67 if (AVR::GPR8RegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
69 } else if (SrcReg == AVR::SP && AVR::DREGSRegClass.contains(DestReg)) { in copyPhysReg()
71 } else if (DestReg == AVR::SP && AVR::DREGSRegClass.contains(SrcReg)) { in copyPhysReg()
77 BuildMI(MBB, MI, DL, get(Opc), DestReg) in copyPhysReg()
161 unsigned DestReg, int FrameIndex, in loadRegFromStackSlot() argument
188 BuildMI(MBB, MI, DL, get(Opcode), DestReg) in loadRegFromStackSlot()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp163 bool isZExt, unsigned DestReg,
173 unsigned DestReg, bool IsZExt);
822 bool IsZExt, unsigned DestReg, in PPCEmitCmp() argument
948 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg) in PPCEmitCmp()
951 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg) in PPCEmitCmp()
989 unsigned DestReg; in SelectFPTrunc() local
992 DestReg = createResultReg(&PPC::GPRCRegClass); in SelectFPTrunc()
994 TII.get(PPC::EFSCFD), DestReg) in SelectFPTrunc()
997 DestReg = createResultReg(&PPC::VSSRCRegClass); in SelectFPTrunc()
999 TII.get(PPC::XSRSP), DestReg) in SelectFPTrunc()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrInfo.cpp58 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
64 Register::isVirtualRegister(DestReg) in copyPhysReg()
65 ? MRI.getRegClass(DestReg) in copyPhysReg()
66 : MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(DestReg); in copyPhysReg()
84 BuildMI(MBB, I, DL, get(CopyOpcode), DestReg) in copyPhysReg()

12345