| /third_party/e2fsprogs/lib/ss/ |
| D | ct_c.sed | 17 # EOR
107 /^;/b EOR
134 /^)/ b EOR
149 : EOR
151 EOR\
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| D | ct_c.awk | 40 /^EOR/ {
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| /third_party/musl/include/arpa/ |
| D | telnet.h | 20 #define EOR 239 macro
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| /third_party/musl/porting/liteos_m_iccarm/kernel/include/arpa/ |
| D | telnet.h | 20 #define EOR 239 macro
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| /third_party/musl/porting/liteos_m/kernel/include/arpa/ |
| D | telnet.h | 20 #define EOR 239 macro
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| /third_party/musl/ndk_musl_include/arpa/ |
| D | telnet.h | 20 #define EOR 239 macro
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| /third_party/musl/porting/uniproton/kernel/include/arpa/ |
| D | telnet.h | 20 #define EOR 239 macro
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedExynosM5.td | 632 def : InstRW<[M5WriteAXW], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)Wrs$")>;
633 def : InstRW<[M5WriteAXX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)Xrs$")>;
690 def : InstRW<[M5WriteLGW], (instregex "^LD(ADD|CLR|EOR|SET|[SU]MAX|[SU]MIN)(A|AL|L)?[BHW]$")>;
691 def : InstRW<[M5WriteLGX], (instregex "^LD(ADD|CLR|EOR|SET|[SU]MAX|[SU]MIN)(A|AL|L)?X$")>;
788 def : InstRW<[M5WriteNALU2], (instregex "^(AND|BIC|EOR|NOT|ORN|ORR)v")>;
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| D | AArch64SchedFalkorDetails.td | 660 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(AND|ORR|ORN|BIC|EOR)v8i8$")>;
724 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(AND|ORR|ORN|BIC|EOR)v16i8$")>;
898 def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^EOR(W|X)r(i|r|s)$")>;
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| D | AArch64SchedExynosM3.td | 496 def : InstRW<[M3WriteAX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)[WX]rs$")>;
616 def : InstRW<[M3WriteNALU1], (instregex "^(AND|BIC|EOR|MVNI|NOT|ORN|ORR)v")>;
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| D | AArch64SchedExynosM4.td | 594 def : InstRW<[M4WriteAX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)[WX]rs$")>;
740 def : InstRW<[M4WriteNALU1], (instregex "^(AND|BIC|EOR|NOT|ORN|ORR)v")>;
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| D | AArch64.td | 216 "CPU fuses AES/PMULL and EOR operations">;
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| D | AArch64SchedCyclone.td | 411 // AND,BIC,CMTST,EOR,ORN,ORR
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| D | AArch64SchedThunderX2T99.td | 1231 // ASIMD logical (AND, BIC, EOR)
1353 (instregex "((AND|ORN|EOR|EON)S?(Xr[rsi]|v16i8|v8i16|v4i32)|" #
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| D | AArch64SchedKryoDetails.td | 435 …(instregex "((AND|ORN|EOR|EON)S?(Wr[rsi]|v8i8|v4i16|v2i32)|(ORR|BIC)S?(Wr[rs]|v8i8|v4i16|v2i32))")…
441 …(instregex "((AND|ORN|EOR|EON)S?(Xr[rsi]|v16i8|v8i16|v4i32)|(ORR|BIC)S?(Xr[rs]|v16i8|v8i16|v4i32))…
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| D | AArch64InstrInfo.td | 1571 defm EOR : LogicalImm<0b10, "eor", xor, "eon">;
1592 defm EOR : LogicalReg<0b10, 0, "eor", xor>;
3948 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;
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| /third_party/flutter/skia/third_party/externals/wuffs/std/lzw/ |
| D | README.md | 100 0x107 RN 0x10F EOR 0x105 R 2 0 2 - EOR
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| /third_party/python/Lib/ |
| D | telnetlib.py | 97 EOR = bytes([25]) # end or record variable
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| /third_party/pcre2/pcre2/src/sljit/ |
| D | sljitNativeARM_32.c | 97 #define EOR 0xe0200000 macro
1247 …return push_inst(compiler, EOR | (flags & SET_FLAGS) | RD(dst) | RN(src1) | ((src2 & SRC2_IMM) ? s… in emit_single_op()
2612 ins = (op == SLJIT_AND ? AND : (op == SLJIT_OR ? ORR : EOR)); in sljit_emit_op_flags()
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| D | sljitNativeARM_64.c | 86 #define EOR 0xca000000 macro
825 FAIL_IF(push_inst(compiler, (EOR ^ inv_bits) | RD(dst) | RN(arg1) | RM(arg2))); in emit_op_imm()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRExpandPseudoInsts.cpp | 1524 auto EOR = buildMI(MBB, MBBI, AVR::EORRdRr) in expand() local
1530 EOR->getOperand(3).setIsDead(); in expand()
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| D | AVRInstrInfo.td | 1753 // Alias for EOR Rd, Rd
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMScheduleSwift.td | 130 // AND,BIC,EOR,ORN,ORR
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| D | ARMScheduleA57.td | 183 // ADD{S}, ADC{S}, ADR, AND{S}, BIC{S}, CMN, CMP, EOR{S}, ORN{S}, ORR{S},
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/DartARM32/ |
| D | assembler_arm.cc | 186 EmitType01(cond, o.type(), EOR, 0, rn, rd, o);
|