| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsInstructionSelector.cpp | 782 MachineInstr *FCMP = BuildMI(MBB, I, I.getDebugLoc(), TII.get(FCMPOpcode)) in select() local
786 if (!constrainSelectedInstRegOperands(*FCMP, TII, TRI, RBI)) in select()
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| /third_party/mesa3d/src/panfrost/bifrost/valhall/test/ |
| D | assembler-cases.txt | 92 43 42 c0 90 01 c2 f5 00 FCMP.v2f16.gt.m1 r2, `r3.h10, `r2.h00, 0x0
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.h | 61 FCMP, enumerator
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| D | SystemZOperators.td | 260 def z_fcmp : SDNode<"SystemZISD::FCMP", SDT_ZCmp>;
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| D | SystemZISelLowering.cpp | 2541 C.Opcode = SystemZISD::FCMP; in getCmp()
5311 OPCODE(FCMP); in getTargetNodeName()
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| /third_party/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_target_gv100.cpp | 116 OPINFO(FCMP , R , NONE, RIC , NONE, RIC , NONE); //XXX: use FSEL for mods
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 68 FCMP, enumerator
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| D | AArch64SchedCyclone.td | 462 // FCMP,FCMPE,FCCMP,FCCMPE
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| D | AArch64SchedFalkorDetails.td | 1115 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^FCMP(E)?(S|D)r(r|i)$")>;
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| D | AArch64ISelLowering.cpp | 1259 case AArch64ISD::FCMP: return "AArch64ISD::FCMP"; in getTargetNodeName()
1719 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS); in emitComparison()
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| D | AArch64InstrInfo.td | 422 def AArch64fcmp : SDNode<"AArch64ISD::FCMP", SDT_AArch64FCmp>;
3552 defm FCMP : FPComparison<0, "fcmp", AArch64any_fcmp>;
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| /third_party/mesa3d/src/broadcom/compiler/ |
| D | v3d_compiler.h | 1312 VIR_A_ALU2(FCMP) in VIR_A_ALU2()
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| /third_party/pcre2/pcre2/src/sljit/ |
| D | sljitNativeARM_64.c | 90 #define FCMP 0x1e602000 macro
1495 return push_inst(compiler, (FCMP ^ inv_bits) | VN(src1) | VM(src2)); in sljit_emit_fop1_cmp()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 4005 MachineInstrBuilder FCMP = in lowerFPTOUI() local
4007 MIRBuilder.buildSelect(Dst, FCMP, FPTOSI, Res); in lowerFPTOUI()
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| /third_party/mesa3d/docs/relnotes/ |
| D | 20.1.0.rst | 738 - pan/bi: Add FCMP.GL.v2f16 on ADD opcode
743 - pan/bi: Structify FMA FCMP
744 - pan/bi Strucitfy ADD FCMP 32
751 - pan/bi: Pack FMA 32 FCMP
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| D | 21.2.0.rst | 837 - pan/bi: Schedule FCMP.v2f16 with abs modifier
838 - pan/bi: Fuse abs into FCMP/FMIN/FMAX.v2f16
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| D | 21.3.0.rst | 385 - pan/bi: Unit test DISCARD+FCMP fusing
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcInstrInfo.td | 1294 // Note 2: the result of a FCMP is not available until the 2nd cycle
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenFastISel.inc | 5461 // FastEmit functions for AArch64ISD::FCMP.
9793 …case AArch64ISD::FCMP: return fastEmit_AArch64ISD_FCMP_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKil…
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