| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZScheduleZ196.td | 83 def : WriteRes<FPU, [Z196_FPUnit]>;
88 def : WriteRes<!cast<SchedWrite>("FPU"#Num), [Z196_FPUnit]>;
718 def : InstRW<[WLat9, WLat9, FPU, NormalGr], (instregex "LT(E|D)BR$")>;
719 def : InstRW<[WLat9, FPU, NormalGr], (instregex "LT(E|D)BRCompare$")>;
744 def : InstRW<[WLat7, FPU, NormalGr], (instregex "LEDBR(A)?$")>;
748 def : InstRW<[WLat7LSU, FPU, LSU, NormalGr], (instregex "LDEB$")>;
749 def : InstRW<[WLat7, FPU, NormalGr], (instregex "LDEBR$")>;
754 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "C(E|D)(F|G)BR(A)?$")>;
756 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "CEL(F|G)BR$")>;
757 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "CDL(F|G)BR$")>;
[all …]
|
| D | SystemZScheduleZEC12.td | 84 def : WriteRes<FPU, [ZEC12_FPUnit]>;
89 def : WriteRes<!cast<SchedWrite>("FPU"#Num), [ZEC12_FPUnit]>;
756 def : InstRW<[WLat9, WLat9, FPU, NormalGr], (instregex "LT(E|D)BR$")>;
757 def : InstRW<[WLat9, FPU, NormalGr], (instregex "LT(E|D)BRCompare$")>;
782 def : InstRW<[WLat7, FPU, NormalGr], (instregex "LEDBR(A)?$")>;
786 def : InstRW<[WLat7LSU, FPU, LSU, NormalGr], (instregex "LDEB$")>;
787 def : InstRW<[WLat7, FPU, NormalGr], (instregex "LDEBR$")>;
792 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "C(E|D)(F|G)BR(A)?$")>;
794 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "CEL(F|G)BR$")>;
795 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "CDL(F|G)BR$")>;
[all …]
|
| D | SystemZSchedule.td | 52 def "FPU"#Num : SchedWrite;
|
| /third_party/boost/libs/context/src/asm/ |
| D | jump_arm_aapcs_elf_gas.S | 53 @ prepare stack for FPU
70 @ prepare stack for FPU
|
| D | ontop_arm_aapcs_elf_gas.S | 53 @ prepare stack for FPU
73 @ prepare stack for FPU
|
| D | jump_arm_aapcs_macho_gas.S | 59 @ prepare stack for FPU
76 @ prepare stack for FPU
|
| D | ontop_arm_aapcs_macho_gas.S | 59 @ prepare stack for FPU
76 @ prepare stack for FPU
|
| D | jump_arm64_aapcs_macho_gas.S | 58 ; prepare stack for GP + FPU
106 ; restore stack from GP + FPU
|
| D | ontop_arm64_aapcs_macho_gas.S | 58 ; prepare stack for GP + FPU
104 ; restore stack from GP + FPU
|
| D | ontop_arm64_aapcs_elf_gas.S | 60 # prepare stack for GP + FPU
106 # restore stack from GP + FPU
|
| D | jump_arm64_aapcs_elf_gas.S | 60 # prepare stack for GP + FPU
108 # restore stack from GP + FPU
|
| D | ontop_riscv64_sysv_elf_gas.S | 66 # prepare stack for GP + FPU
142 # restore stack from GP + FPU
|
| D | jump_riscv64_sysv_elf_gas.S | 66 # prepare stack for GP + FPU
144 # restore stack from GP + FPU
|
| /third_party/musl/ |
| D | INSTALL | 60 * Default ABI variant uses FPU registers; alternate soft-float ABI
61 that does not use FPU registers or instructions is available
69 * Default ABI variant uses FPU registers; alternate soft-float ABI
70 that does not use FPU registers or instructions is available
90 * Full FPU ABI or soft-float ABI is supported, but the
91 single-precision-only FPU ABI is not
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMELFStreamer.cpp | 98 void emitFPU(unsigned FPU) override;
233 void ARMTargetAsmStreamer::emitFPU(unsigned FPU) { in emitFPU() argument
234 OS << "\t.fpu\t" << ARM::getFPUName(FPU) << "\n"; in emitFPU()
305 unsigned FPU = ARM::FK_INVALID; member in __anon7f2171200111::ARMTargetELFStreamer
409 void emitFPU(unsigned FPU) override;
903 FPU = Value; in emitFPU()
907 switch (FPU) { in emitFPUDefaultAttributes()
1033 report_fatal_error("Unknown FPU: " + Twine(FPU)); in emitFPUDefaultAttributes()
1072 if (FPU != ARM::FK_INVALID) in finishAttributeSection()
1135 FPU = ARM::FK_INVALID; in finishAttributeSection()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Support/ |
| D | ARMTargetParser.cpp | 252 unsigned ARM::parseFPU(StringRef FPU) { in parseFPU() argument
253 StringRef Syn = getFPUSynonym(FPU); in parseFPU()
324 StringRef ARM::getFPUSynonym(StringRef FPU) { in getFPUSynonym() argument
325 return StringSwitch<StringRef>(FPU) in getFPUSynonym()
338 .Default(FPU); in getFPUSynonym()
|
| /third_party/ffmpeg/libavutil/arm/ |
| D | asm.S | 44 # define FPU macro
46 # define FPU @ macro
71 FPU .fpu neon label
75 FPU .fpu vfp label
|
| /third_party/boost/libs/math/doc/overview/ |
| D | config_macros.qbk | 32 [[`BOOST_FPU_EXCEPTION_GUARD`] [Used at the entrypoint to each special function to reset all FPU ex…
34 on platforms or hardware that behave strangely if any FPU exception flags are set when calling stan…
41 [[`BOOST_MATH_INSTRUMENT_FPU`] [Output the state of the FPU's control flags.]]
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsRegisterInfo.td | 49 // Mips 32-bit FPU Registers
52 // Mips 64-bit (aliased) FPU Registers
154 /// Mips Single point precision FPU Registers
162 /// Mips Double point precision FPU Registers (aliased
169 /// Mips Double point precision FPU Registers in MFP64 mode.
175 /// MSA and FPU cannot both be present unless the FPU has 64-bit registers
428 // MIPS32r6/MIPS64r6 store FPU condition codes in normal FGR registers.
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/ |
| D | ARMTargetParser.h | 247 StringRef getFPUSynonym(StringRef FPU);
252 unsigned parseFPU(StringRef FPU);
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCScheduleP8.td | 27 // 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
41 // The Floating-Point Unit (FPU) and Vector Media Extension (VMX) units
44 // FPU, so keep in mind that FPU==VSU.
394 // to 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
|
| /third_party/mindspore/mindspore/lite/micro/example/mnist_stm32f746/ |
| D | Makefile | 115 FPU = -mfpu=fpv5-sp-d16 macro
121 MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI)
|
| /third_party/boost/libs/coroutine/doc/ |
| D | coroutine.qbk | 75 FPU registers for performance reasons.
77 [note According to the calling convention the FPU registers are preserved by
|
| /third_party/pixman/pixman/ |
| D | solaris-hwcap.mapfile | 30 hwcap_1 = V0x0 FPU OVERRIDE;
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ScheduleBdVer2.td | 61 // Four FPU pipes.
63 def PdFPU0 : ProcResource<1>; // Vector/FPU Pipe0
64 def PdFPU1 : ProcResource<1>; // Vector/FPU Pipe1
65 def PdFPU2 : ProcResource<1>; // Vector/FPU Pipe2
66 def PdFPU3 : ProcResource<1>; // Vector/FPU Pipe3
68 // FPU grouping
108 // FPU Pipeline Scheduling
111 // The FPU unit is shared between the two cores.
|